Lab modules
AXL-003 — Fast waveform generator PMOD module (8-bit R-2R DAC)
Catalog #3 in the AruviX lab line, level L4 (instrument). Pairs with AXL-002 as its own test source; DDS at MHz rates where the MCP4725 lab (axo-010) tops out at audio.
Circuit review & bench-test guide →
Components#
Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.
| Ref | Value | What it does on this board | Part number | Footprint |
|---|---|---|---|---|
C1 |
100nF 16V X7R | U1 op-amp decoupling | GRM188R71C104KA01DMurata |
C_0603_1608Metric |
C2 |
10uF 10V X5R | U1 bulk decoupling (fast edges into capacitive loads) | GRM21BR61A106KE19LMurata |
C_0805_2012Metric |
J1 |
PMOD PLUG 2x6 | PMOD peripheral plug (Digilent spec 1.2) | not selected generic |
PinHeader_2x06_P2.54mm_Horizontal |
J2 |
WAVE OUT | Waveform output header: 1 signal, 2 GND (parallel with the BNC) | not selected generic |
PinHeader_1x02_P2.54mm_Vertical |
J3 |
BNC | BNC output, parallel with J2 (stock footprint verified) | B6252HB-NPP3G-50Amphenol RF Datasheet ↗ |
BNC_Amphenol_B6252HB-NPP3G-50_Horizontal |
R1 |
2k 1% | R-2R bit leg for D0 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R2 |
2k 1% | R-2R bit leg for D1 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R3 |
2k 1% | R-2R bit leg for D2 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R4 |
2k 1% | R-2R bit leg for D3 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R5 |
2k 1% | R-2R bit leg for D4 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R6 |
2k 1% | R-2R bit leg for D5 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R7 |
2k 1% | R-2R bit leg for D6 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R8 |
2k 1% | R-2R bit leg for D7 (2R) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R9 |
1k 1% | R-2R chain resistor LAD0 -> LAD1 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R10 |
1k 1% | R-2R chain resistor LAD1 -> LAD2 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R11 |
1k 1% | R-2R chain resistor LAD2 -> LAD3 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R12 |
1k 1% | R-2R chain resistor LAD3 -> LAD4 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R13 |
1k 1% | R-2R chain resistor LAD4 -> LAD5 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R14 |
1k 1% | R-2R chain resistor LAD5 -> LAD6 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R15 |
1k 1% | R-2R chain resistor LAD6 -> LAD7 (R) | RC0603FR-071KLYageo Datasheet ↗ |
R_0603_1608Metric |
R16 |
2k 1% | R-2R LSB terminator (2R to GND) | RC0603FR-072KLYageo Datasheet ↗ |
R_0603_1608Metric |
R17 |
100R | Series back-termination / short-circuit protection on the output | RC0603FR-07100RLYageo Datasheet ↗ |
R_0603_1608Metric |
U1 |
OPA356 | 200 MHz CMOS rail-to-rail op-amp, unity buffer on the ladder output | OPA356AIDRTexas Instruments Datasheet ↗ |
SOIC-8_3.9x4.9mm_P1.27mm |
Signals#
Net labels used in the schematic, which are also the names the HDL top level should use.
3V3 D0 D1 D2 D3 D4 D5 D6 D7 GND LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 WAVE_BUF WAVE_OUT
Production status#
| Schematic ERC | 0 violations |
|---|---|
| PCB layout | complete |
| DRC | 0 violations |
| Fab package | exported (24 gerbers + drill + CPL + BOM) |
| Fabricated | no — design stage only |
Source: boards/lab-modules/axl-003-wavegen
Catalog #3 in the AruviX lab line (../README.md), level L4 (instrument). Pairs with AXL-002 as its own test source; DDS at MHz rates where the MCP4725 lab (axo-010) tops out at audio.
Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.
What it teaches#
The dds_fast core: a phase accumulator + waveform table driving a parallel DAC every fabric clock. Update-rate math: at a 25 MHz sample clock, Nyquist allows <12.5 MHz, but with only ~2.5 samples per cycle and ladder/buffer settling, ~10 MHz is the usable ceiling — measure the roll-off and the images on AXL-002. Second lesson: R-2R accuracy vs resistor tolerance — with 1% parts the MSB leg error alone can reach ~2 LSB at 8 bits; measure INL/DNL and see why real DACs use trimmed networks.
Design#
- R-2R ladder, R = 1 kΩ / 2R = 2 kΩ (both E24, 1%, 0603, Yageo RC0603FR-071KL / RC0603FR-072KL): 8× 2k bit legs, 7× 1k chain, 1× 2k LSB terminator = 16 resistors. Full scale 0–3.3 V.
- D0–D7 are host-driven, so no series resistors on the data lines (line rule applies to module-driven lines only).
- OPA356AIDR unity buffer (SOIC-8 D variant; +in from ladder, −in tied to out) — the review-recommended R-2R buffer (200 MHz CMOS RRIO, stock symbol + footprint). 100 nF + 10 µF decoupling.
- Output through 100 Ω (back-termination / short protection) to a 1×02 header and a BNC (
BNC_Amphenol_B6252HB-NPP3G-50_Horizontal, stock footprint verified — same check as AXL-002, so the BNC is fitted).
| PMOD pin | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Net | D0 | D1 | D2 | D3 | GND | 3V3 | D4 | D5 | D6 | D7 | GND | 3V3 |
Regenerate#
python3 generate_design.py
Remaining for release#
- [ ] PCB layout (keep ladder legs matched-length), DRC, fab outputs
- [ ]
hdl/:dds_fastcore, golden-model testbench, ECP5 demo - [ ] BOM export and availability check, design-review checklist