← AXC-003

Circuit review & bench-test guide

AXC-003 — ESP32-C3 WiFi/BLE co-processor PMOD module

Document purpose#

This document explains the axc-003-wifi PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC report in reports/.

This board has never been fabricated. Repository status is schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started; not released. There is no PCB, no BOM export, no DRC record, and no first-article bench result. Every number below is a target to verify against real hardware, not a proven result.

1. What the board does#

The board carries an Espressif ESP32-C3-WROOM-02 module (substituted per the line README for the catalog's ESP32-C3-MINI-1 — same C3 silicon) as a UART AT-command modem: the FPGA stays the brain, the ESP32 is the radio. PMOD Type 3 wiring adds EN (via solder jumper JP1) and GPIO9/BOOT so the host can drop the module into the ROM serial bootloader for reflashing. The SPI-capable GPIOs are routed to a DNP header (J2) so the esp-hosted upgrade is firmware + header only. Power is the board's defining constraint: WiFi TX bursts reach ~350 mA against a PMOD rail that should only be assumed good for ~100 mA, so the module carries 30 µF of local bulk and a JP2 rail-source jumper for external 3.3 V.

Functional block diagram#

PMOD host (3.3 V)             Module
┌────────────────┐   ┌────────────────────────────────────────┐
│ 1 EN_HOST ─────┼──>│ JP1 (bridged) ── EN (R1 10k PU, C1 1µ) │
│ 2 TXD ─────────┼──>│ U1 RX (IO20)      U1 ESP32-C3-WROOM-02 │
│ 3 RXD <───R5───┼───│ U1 TX (IO21)      (PCB antenna ►►      │
│ 4 BOOT ────────┼──>│ GPIO9 (R2 10k PU)  faces off-board)    │
│ 6/12 3V3 ──────┼──>│ JP2 1-2 ─┬─ ESP_3V3                    │
│ 5/11 GND ──────┼───│          │  C2 100n + C3/C4/C5 3×10µ   │
└────────────────┘   │ J3 EXT 3V3 (DNP) ─ JP2 2-3             │
                     │ straps: R3 (IO2), R4 (IO8) 10k PU      │
                     │ J2 (DNP 2×3): IO6/7/2/10 + IO3/4 SPI   │
                     └────────────────────────────────────────┘

2. Safety and scope boundaries#

• Everything is 3.3 V; hazard to people is negligible. The real risks are brownout during WiFi TX (the classic symptom set: resets mid-connect, garbled boot banners, "works until it joins an AP") and boot-strap misunderstandings that make a healthy module look dead.
• The module supply range is 3.0–3.6 V. Never feed 5 V at J3 or the PMOD; there is no regulator on this board.
• This is an intentional radio transmitter (2.4 GHz WiFi/BLE). The WROOM's PCB antenna is part of the module — there is no external antenna to forget, but the antenna-area rules still apply: do not operate it pressed against metal, a ground plane, or a lab chassis; keep the antenna end in free air, or RF performance and TX current both degrade. Duty-cycle/regulatory obligations follow the module's certification — keep the module's shield and antenna unmodified or the certification is void.
• Standalone bench work must use a current-limited 3.3 V supply set to 500 mA — a 100 mA limit will brown the module out during TX and produce misleading failures.
• Verify the host PMOD 3.3 V budget before long TX sessions (line rule); the ECP5 rev-A rail measurement is an explicit open item in the README.
• ERC-clean is a schematic check only; the antenna keep-out and bulk-cap placement are layout promises, not facts.

3. Power and boot sequence#

1. ESP_3V3 comes from PMOD 3V3 through JP2 1-2 (default) or from J3 external 3.3 V through JP2 2-3. Cutting the 1-2 side fully isolates the PMOD 3V3 pin. C2 (100 nF) + C3/C4/C5 (3 × 10 µF) buffer TX bursts.
2. EN rises through R1 (10 k) delayed/deglitched by C1 (1 µF); with JP1 bridged (default) the host can also drive EN via PMOD pin 1.
3. Boot-mode straps sample while EN rises: GPIO9 (BOOT) high via R2 → normal SPI-flash boot; GPIO2 high via R3 and GPIO8 high via R4 — both must be 1 for the valid boot modes. Host drives GPIO9 low and pulses EN low → ROM serial download mode for flashing.
4. In normal boot the AT firmware starts, prints a boot banner on its UART, and answers the AT command set at 115200 8N1 (AT firmware default).
5. FPGA TXD (PMOD pin 2) drives ESP RX (IO20) directly; ESP TX (IO21) reaches PMOD pin 3 through R5 (100 Ω).
6. On AT+CWJAP (join AP) the radio transmits: current bursts to ~350 mA. This is where thin rails fail.

4. Interfaces#

There are no test points defined yet; bench probing is at J1/J2/J3 pins, the jumpers, and the WROOM castellations.

5. Component-by-component review#

5.1 Module and expansion#

5.2 Straps, EN network, and UART conditioning#

5.3 Power selection and bulk#

Every ref-des is covered: U1, J1, J2, J3, JP1, JP2, R1–R5, C1–C5.

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Confirm JP1 bridged, JP2 bridged 1-2, J2/J3 DNP for the default build.
• Verify R2/R3/R4 land on GPIO9/GPIO2/GPIO8 respectively (strap identity matters, not just "three pull-ups somewhere").
• Verify R5 sits in the ESP-TX→host-RXD path and the host-TXD path is direct.
• Confirm C3/C4/C5 are the 10 µF parts and (at layout) sit tight to the module's 3V3 castellation.
• Layout (future): antenna end overhangs or faces off-board, no copper/ pour under the antenna area per the WROOM keep-out figure, J3 polarity silkscreened.
• Confirm host gateware: pin 1 and pin 4 are outputs only when deliberately sequencing reset/boot; idle them high-Z or high.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, module lot/marking, AT firmware version, and supply identity.

A. Unpowered inspection and resistance tests#

1. Visual inspection: WROOM castellations, jumper states, passive bank.
2. DMM: rail resistance both polarities; JP2 1-2 continuity; strap nodes to 3V3 ≈ 10 k; J1 pin 3 to ESP TX castellation ≈ 100 Ω.

B. Standalone power-on (bench supply, 3.3 V, 500 mA limit)#

1. Feed J1 pins 6/5 (or J3 with JP2 2-3). Watch current: expect a brief inrush, then tens of mA. No heating.
2. Scope ESP TX (module side of R5): boot banner burst at power-on. A 115200 banner proves the module, rail, EN network, and straps in one shot. If the banner is ROM-only gibberish ending in a boot-mode error, check the strap levels before suspecting the module.

C. AT firmware first contact (USB-UART, still no FPGA)#

1. Attach a 3.3 V USB-UART: RX to J1 pin 3, TX to J1 pin 2, GND common.
2. Power-cycle; capture the banner. Then send AT → expect OK, and AT+GMR → record every version line in the bench record.
3. If there is no banner and no AT response: enter download mode (hold J1 pin 4 low, pulse EN low via pin 1, release pin 4), confirm the ROM loader banner, and flash the ESP-AT release for WROOM-02. A blank module is expected from some vendors — this step is bring-up, not repair.
4. AT+CWLAP: scan and record APs/RSSI. This is the first real RF test.

D. TX current and brownout characterization (the board's core test)#

1. Insert a current probe or 0.1 Ω shunt in the 3.3 V feed; scope the shunt and ESP_3V3 (at C3–C5) simultaneously.
2. AT+CWJAP="ssid","pass": capture the association burst. Expect peaks toward ~350 mA; record actual peak, duration, and the minimum ESP_3V3 voltage. ESP_3V3 must stay above 3.0 V.
3. Run sustained traffic (e.g. AT+PING loop or a TCP send loop) for 10 minutes; record droop and any resets.
4. Deliberately reproduce the brownout signature once for the record: set the bench limit to 100 mA and attempt AT+CWJAP. Document the symptoms (reset banner mid-association, WIFI DISCONNECT, garbled output) so field failures are recognizable. Restore 500 mA after.

E. Hosted bring-up (FPGA PMOD host)#

1. Measure the host rail: scope PMOD 3V3 at the module during a repeat of D.2 before trusting long TX sessions — this is the README's open ECP5 budget item. If droop approaches 3.0 V, move to JP2 2-3 + J3 external feed and record the decision.
2. Fabric UART at 115200: repeat AT/AT+GMR/AT+CWLAP through the FPGA; compare against a parallel USB-UART tap.
3. Exercise host-controlled reset (pin 1) and download-mode entry (pins 1+4) from gateware; confirm re-flash works through the PMOD.
4. Run the MQTT/cloud lesson flow end to end (join, publish, disconnect) with current logging.

F. Robustness checks#

1. 50 power cycles with association each time; count failures.
2. JP2 2-3 external-feed configuration: verify isolation (PMOD 3V3 pin shows no connection to ESP_3V3) and repeat D.2.
3. Range/orientation sanity: RSSI vs antenna orientation, and confirm no metal within ~10 mm of the antenna end during all tests.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is small but every part of it exists for a boot or power reason: three strap pull-ups and the EN RC decide whether the module boots at all, and the 30 µF bulk plus the JP2/J3 external-feed path decide whether it survives its own transmitter. The single most valuable bench activity is the shunt-and-scope TX capture in 9.D — it converts the line's "~350 mA vs ~100 mA PMOD budget" warning from folklore into a measured number for this host, and the deliberate brownout reproduction gives field debugging a reference signature. Open risks: no PCB exists (antenna keep-out and bulk placement are promises), the ECP5 rail budget is unmeasured, purchased modules may ship without AT firmware, and the J2 esp-hosted pin roles are firmware-defined and unverified.