← AXC-002

Circuit review & bench-test guide

AXC-002 — LAN8720A RMII Ethernet PHY dual-PMOD module

Document purpose#

This document explains the axc-002-ethernet-phy dual-PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC report in reports/.

This board has never been fabricated. Repository status is schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started; not released. There is no PCB, no BOM export, no DRC record, and no first-article bench result. The design was cross-checked against the Microchip LAN8720A schematic checklist and the EVB8720 pattern, but every number below is a target to verify against real hardware, not a proven result.

1. What the board does#

The board is the fabric flagship of the W5500/LAN8720 paired lesson: a bare Microchip LAN8720A 10/100 PHY on RMII (50 MHz), so the MAC, ARP, ICMP, and UDP live in the FPGA. It spans two adjacent PMOD sockets on 0.9-inch centers: J1 carries the RMII data group, J3 carries MDIO/MDC-adjacent management, REF_CLK, ~INT, and ~RST. The same Hanrun HR911105A MagJack as AXC-001 carries the MDI side. A solder jumper (JP1) selects the REF_CLK topology: host-PLL-driven (default) or on-board 50 MHz oscillator (DNP).

Functional block diagram#

PMOD host (3.3 V)              Module                            Network
┌───────────────────┐   ┌───────────────────────────────┐   ┌─────────────┐
│ J1: TXD0/1, TX_EN─┼──>│ direct        U1 LAN8720A TX±─┼──>│ J2          │
│ J1: RXD0/1,CRS_DV,│<──┼─100Ω (R14–17)─ (RMII PHY) RX±<┼───│ HR911105A   │
│     RX_ER         │   │                               │   │ (center taps│
│ J1: MDC ──────────┼──>│ MDC     straps R6–R11 (10k)   │   │  → 3V3A +   │
│ J3.1 MDIO <──────>┼───│ MDIO (R12 1.5k PU)            │   │  C1/C2;     │
│ J3.2 REF_CLK ─────┼─┬>│ JP1 1-2 ──> XTAL1/CLKIN       │   │  LEDs NC)   │
│ J3.3 ~INT <──R18──┼─│─│ nINT    RBIAS: R5 12.1k 1%    │   └─────────────┘
│ J3.4 ~RST ────────┼─│>│ nRST (R13 10k PU)             │
└───────────────────┘ │ │ U2 50 MHz osc (DNP) ──JP1 2-3 │
              R19(DNP)└─│───────── OSC_OUT              │
                        │ VDDCR: C4 1µ + C5 470p        │
                        │ FB1 → 3V3A; R1–R4 49.9Ω       │
                        └───────────────────────────────┘

2. Safety and scope boundaries#

• Everything is 3.3 V; hazard to people is negligible. The real risks are strap-latch mistakes (the PHY silently boots into the wrong mode), clock-topology confusion at JP1 (two drivers on one net if both jumper sides are bridged), and VQFN-24 assembly quality.
• Never bridge both JP1 positions. JP1 2-3 with U2 fitted while the host also drives J3 pin 2 puts two push-pull drivers on REF_CLK — R19 limits but does not remove the contention. Decide the topology before plugging into a host, and make the host gateware match.
• The module needs both adjacent host PMOD sockets on exact 0.9 in centers; forcing it into one socket bends pins and cross-powers nets.
• RMII is sampled at 50 MHz: use the host's high-speed (no series-R) PMOD socket if fitted, and expect marginal behavior on long-lead probing.
• Ethernet is transformer-isolated at J2; a live switch is safe. No PoE until the chassis arrangement is reviewed.
• Standalone bench work uses a current-limited 3.3 V supply (150 mA limit; the PHY draws ~40–60 mA class with link up).
• ERC-clean is a schematic check only; no PCB exists. The 50 MHz route, MDI matching, and dual-plug mechanics are unbuilt and unverified.

3. Power, strap, and clock sequence#

1. 3V3 arrives from the host (both plugs' pins 6/12) or the bench supply. FB1 derives 3V3A; C3/C6/C7 (100 nF) and C8/C9 (10 µF) decouple.
2. REGOFF is strapped low (R11), so the internal 1.2 V core regulator runs; C4 (1 µF) + C5 (470 pF) on VDDCR are the datasheet values.
3. 50 MHz reaches XTAL1/CLKIN: default JP1 1-2 from the host PLL via J3 pin 2; alternative JP1 2-3 from U2 (DNP oscillator), which also feeds the host through R19 (DNP, fit with U2) so the host can slave.
4. Strap latch: on the rising edge of ~RST the PHY samples the strap pins: MODE[2:0] = 111 (R6/R7/R8 pull-ups on RXD0/RXD1/CRS_DV → all-capable autonegotiation), PHYAD0 = 0 (R9 pull-down on RX_ER → PHY address 0), nINTSEL = 1 (R10 → pin 14 is ~INT, not REFCLKO), REGOFF = 0 (R11). The host must not drive these lines low/high against the straps while ~RST rises — after latch they become ordinary RMII outputs.
5. The PHY autonegotiates. Management runs over MDIO (R12 1.5 kΩ pull-up, per datasheet) clocked by MDC from J1 pin 10.
6. RMII traffic flows: TXD0/TXD1/TX_EN host→PHY direct; RXD0/RXD1/CRS_DV/ RX_ER PHY→host through 100 Ω (R14–R17); ~INT through R18.

4. Interfaces#

There are no test points defined yet (no layout exists); bench probing is at the PMOD pins, passives, and VQFN pins/pads.

5. Component-by-component review#

The board is dense (~28 nets), so components are grouped by function.

5.1 PHY, jack, and clock source#

5.2 Straps and bias (all latch on the ~RST rising edge)#

5.3 MDI termination, RMII series, and decoupling#

Every ref-des on the board is covered above: U1, U2, J1, J2, J3, JP1, FB1, R1–R19, C1–C9.

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Verify U1 orientation and the VQFN-24 exposed pad soldering (X-ray if available).
• Buzz every strap resistor to its exact pin: R6→RXD0, R7→RXD1, R8→CRS_DV, R9→RX_ER(GND), R10→nINTSEL, R11→REGOFF(GND). A swapped pull direction is a silent mode change.
• Measure R5 = 12.1 kΩ 1 % and R12 = 1.5 kΩ before power.
• Confirm the jack LED pins are unconnected and stay that way.
• Confirm both J2 center taps reach 3V3A and C1/C2 sit at the taps.
• Buzz TXP/TXN/RXP/RXN U1↔J2 for pair swaps.
• Verify JP1 state matches the intended topology and that U2/R19 are DNP in the default build.
• Verify the two PMOD plugs land on exact 0.9 in centers at layout, and that J3 pin 2 is documented as requiring a clock-capable host pin.
• Confirm host gateware: TXD0/TXD1/TX_EN outputs, everything else on J1 inputs, MDIO bidirectional open-drain, and no host drive on RXD0/RXD1/ CRS_DV/RX_ER around reset (strap latch).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment, link-partner identity, JP1 state, and host clock provenance.

A. Unpowered inspection and resistance tests#

1. Visual inspection: U1, strap bank, termination bank, J2, JP1 state.
2. DMM: rail resistances; RBIAS 12.1 k; MDIO to 3V3 ≈ 1.5 k; each strap resistor value; J1 pin 4 to U1 RXD0 ≈ 100 Ω (R14) and likewise R15–R18 paths.

B. Standalone power-on and strap latch (bench supply, no host)#

1. Feed current-limited 3.3 V into a PMOD 3V3/GND pair. Record current.
2. With no clock and no host, check strap-node DC levels (section 7).
3. Provide 50 MHz to XTAL1 (bench generator through JP1 1-2 path at J3 pin 2, or temporarily fit U2 + JP1 2-3). Verify amplitude/edges at the pin.
4. Strap-latch check at reset: scope RXD0 (any strap line) and ~RST. Pull ~RST low ≥100 µs and release; confirm the strap line sits at its strap level while ~RST rises, then switches to RMII output behavior. Repeat with the intended host attached later — a host that drives these lines during reset corrupts the latch.

C. MDIO bring-up (bench master or FPGA, low risk first)#

1. Bit-bang MDC/MDIO (any 3.3 V GPIO pair; MDC ≤2.5 MHz to start).
2. Read registers 2 and 3 at PHY address 0: expect 0x0007 and 0xC0Fx. Repeat 100×. Reads of 0xFFFF mean address/pull-up/wiring problems; this gate must be bulletproof before anything else.
3. Read register 1 twice (link status is latch-low): no cable → link down.
4. Attach a cable to a live switch: register 1 link bit within ~2 s; read register 5 (LPA) and record the partner's advertised abilities.
5. Autonegotiation matrix: force the partner to 10/half, 10/full, 100/half, 100/full; confirm the resolved mode each time (reg 31 special-modes / vendor status register).

D. RMII signal capture (still hostless or with passive host)#

1. With link up and the partner sending traffic (e.g. broadcast-rich network or a ping flood at the PHY's MAC-less carcass — frames will die in fabric later, the PHY still forwards them), capture CRS_DV and RXD[1:0] with a ≥200 MS/s logic analyzer against REF_CLK.
2. Expected: CRS_DV asserts per frame; preamble 0x55… nibble pattern on RXD; data changes on REF_CLK edges with usable setup/hold at 50 MHz. Record eye/timing margins — this is the calibration data the rmii_mac core's constraints will be checked against.
3. RX_ER should stay low on a clean link; note any assertions.

E. Hosted bring-up (FPGA host, both sockets)#

1. Confirm host PLL provides 50 MHz ±50 ppm on J3.2 (JP1 1-2) before plugging in, and that gateware tristates strap lines through reset.
2. Plug into both sockets. Re-run the MDIO PHY-ID gate through fabric.
3. Bring up rmii_mac RX: capture real frames into a fabric FIFO; verify CRC32 against Wireshark on the partner, byte-for-byte.
4. Bring up TX: send a fixed UDP/ARP frame; verify on the partner.
5. Link partner test: repeat against at least two different switches and one direct-to-NIC connection (auto-MDIX); record negotiation results and error counters over a 30-minute soak.
6. If the oscillator topology is wanted: power down, fit U2 + R19, cut JP1 1-2, bridge 2-3, reconfigure the host to receive REF_CLK, and repeat steps 2–5. Never run with both topologies half-configured.

F. Release-only tests#

EMC, ESD to the jack, chassis-split decision, long-cable/interop sweeps, and 50 MHz clock-quality characterization across temperature are controlled-lab work.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful implementation of the Microchip checklist: correct strap plan (with the LED/strap conflict consciously resolved by leaving the jack LEDs dark), datasheet RBIAS/VDDCR/MDIO values, EVB8720 center-tap termination, and a defensible answer to the line's REF_CLK open decision via JP1. The design's sharp edges are all dynamic: strap levels must survive the ~RST rising edge against whatever the host drives, the 50 MHz clock must be PLL-clean in the default topology, and JP1 must never be double-bridged. The PHY-ID read (0x0007/0xC0Fx) is the bring-up gate; the RMII capture in 9.D is what turns this board from "links up" into usable calibration data for the rmii_mac core. No PCB exists, the dual-plug mechanics and 50 MHz routing are unverified, and both oscillator MPNs are still TBD.