Comms modules

AXC-002 — LAN8720A RMII Ethernet PHY dual-PMOD module

Catalog #2 in the AruviX comms line, level L5 (RMII, 50 MHz). The fabric flagship of the W5500/LAN8720 paired lesson: a bare 10/100 PHY, so the MAC, ARP, ICMP, and UDP live in the FPGA — then a real network stack in AruviOS. Same Hanrun HR911105A MagJack as AXC-001 to amortize RJ45 sourcing.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 3V3A CRS_DV GND INT_N MDC MDIO NINTSEL OSC_OUT PHY_CLKIN PHY_CRS_DV PHY_INT_N PHY_RXD0 PHY_RXD1 PHY_RXER RBIAS REF_CLK REGOFF RST_N RXD0 RXD1 RXN RXP RX_ER TXD0 TXD1 TXN TXP TX_EN VDDCR

Production status#

Source: boards/comms-modules/axc-002-ethernet-phy

Catalog #2 in the AruviX comms line (../README.md), level L5 (RMII, 50 MHz). The fabric flagship of the W5500/LAN8720 paired lesson: a bare 10/100 PHY, so the MAC, ARP, ICMP, and UDP live in the FPGA — then a real network stack in AruviOS. Same Hanrun HR911105A MagJack as AXC-001 to amortize RJ45 sourcing.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

rmii_mac (tx/rx + CRC32) in fabric, MDIO management frames, clocking discipline at 50 MHz, and the fabric-ping graduation exercise (answer ICMP echo entirely in Verilog). Uses the same upper-layer interfaces as AXC-001 so students can swap controllers.

Design#

• Dual PMOD on 0.9 in centers (Digilent spec 1.2.0): J1 = RMII data (TXD0/TXD1/TX_EN host→PHY direct; RXD0/RXD1/CRS_DV/RX_ER PHY→host via 100 Ω), J3 = MDIO (1.5 kΩ pull-up per datasheet), REF_CLK, ~INT (100 Ω), ~RST (10 k pull-up).
• REF_CLK topology (line README open decision, resolved as the solder jumper): JP1 1-2 (default) = host FPGA PLL drives 50 MHz on J3 pin 2 into XTAL1/CLKIN; JP1 2-3 = on-board 50 MHz oscillator (Abracon ASE 3225, DNP) drives XTAL1 and, through R19 (100 Ω, DNP, fit with U2), J3 pin 2 so the host can slave. J3 pin 2 must be a clock-capable host pin.
• Straps, all 10 k per the LAN8720A datasheet/schematic checklist: MODE[2:0] high (all-capable auto-negotiation), PHYAD0 low (address 0), nINTSEL high (pin 14 = ~INT, not REFCLKO), REGOFF low (internal 1.2 V regulator on). Strap levels latch on the ~RST rising edge.
• RBIAS 12.1 kΩ 1 % to GND; VDDCR 1 µF + 470 pF (datasheet values).
• MDI: 49.9 Ω 1 % pull-ups to 3V3A on all four lines; both MagJack center taps tied to 3V3A with 100 nF decoupling at the taps (EVB8720 pattern).
• Jack LEDs left unconnected: LAN8720A LED1/LED2 double as REGOFF/nINTSEL straps and LED wiring would fight the chosen strap levels (classic LAN8720 gotcha, documented on the schematic).
• 3V3 → 3V3A ferrite bead; RMII sampled at 50 MHz — prefer the host's high-speed (no series-R) PMOD socket if fitted.

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (dual plugs on exact 0.9 in centers, 50 MHz clock route, MDI pairs matched), DRC, fab outputs
• [ ] Pin the DNP oscillator MPN (ASE-50.000MHZ class)
• [ ] hdl/: rmii_mac + arp_icmp_udp cores, packet-level golden-model testbenches, ECP5 fabric-ping demo
• [ ] BOM export and availability check, design-review checklist