← AXA-011

Circuit review & bench-test guide

AXA-011 — RS-485 node PMOD module

Document purpose#

This document explains the axa-011-rs485 PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py), the module README, the actuator-line overview in ../README.md, and the MAX3485 family datasheet.

The board is an unfabricated prototype design. Repository status: schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, no board built, no HDL delivered, and no bench evidence of any kind. Every value below is a design target or a datasheet number to verify against a future assembled board, not proof that a board works. The manufacturing BOM, layout, and DRC evidence that the sibling USB-C guides lean on do not exist yet for this module.

1. What the board does#

The board is a half-duplex RS-485 bus node. A MAX3485 3.3 V transceiver converts the FPGA's single-ended UART (TXD/RXD on PMOD Type 3 UART positions) to the differential A/B pair on a 3-position screw terminal, with the host FPGA also owning the driver-enable (DE) turnaround. Termination (120 Ω) and fail-safe bias (390 Ω pair) sit behind solder jumpers so one board design serves any position on a multi-drop bus: middle node, bus end, or the single bias master. All jumpers ship open except JP1, which ties ~RE to DE for automatic half-duplex receiver muting.

It contains no UART, no protocol engine, and no isolation. Framing, baud generation, and — the module's teaching point — DE turnaround timing all live in FPGA fabric. Power is 3.3 V from the PMOD only; there is no external power terminal because the transceiver is a logic-class load.

Functional block diagram#

PMOD J1 (Type 3 UART positions)
  1 DE ────────┬────────────────> DE  ┌──────────────┐
               │ R2 10k to GND       │              │  A ──┬──────────> J2.1 A
  2 TXD ────────────────────────> DI  │   MAX3485    │      ├─ JP3+R3 120R ─┐
  3 RXD <── R1 100R ── RS_RO ─── RO  │     U1       │      ├─ JP4+R4 390R to 3V3
  4 RE_HOST ── JP2 (open) ─┐         │  half-duplex │  B ──┼──────┬───> J2.2 B
               JP1 (bridged)├──> ~RE  │  transceiver │      └──────┘
  DE ──────────────────────┘         │              │      └─ JP5+R5 390R to GND
  5/11 GND ──────────────────────────┤ GND          │
  6/12 3V3 ── C1 100nF ──────────────┤ VCC          │  GND ────────> J2.3 GND
                                     └──────────────┘

2. Safety and scope boundaries (actuator-family rules)#

This is a communications board with no motor rail of its own, but it is not exempt from the actuator-line safety conventions, because the bus it drives commands actuator nodes. A bus fault, a wrong bias configuration, or a DE line stuck asserted can start a remote actuator, jam the bus so a stop command never arrives, or corrupt a frame into a different valid command. Treat bus bring-up with the same discipline as a motor driver.

• Current-limited first power. First power-up of any assembled module is from a current-limited 3.3 V source (set roughly 100 mA, matching the PMOD budget). Quiescent draw should be a few milliamps; a board that pulls the limit has an assembly fault.
• Verify bus behavior with NO actuator power applied on any node first. Bring the RS-485 link up, prove idle levels, turnaround, and two-way byte exchange while every remote actuator rail is unpowered or disconnected. Only then energize actuator rails, one node at a time.
• Never rewire A/B while remote actuators are powered. A momentary A/B swap or open inverts or floats the bus; receivers on an unbiased floating pair can chatter, and chatter into a live actuator node is uncommanded motion. De-energize actuator rails before touching bus wiring, jumpers, or terminations.
• Family rail-sequencing convention: logic before actuator rails, on all nodes. Every node's FPGA/logic rail comes up, DE pull-downs take effect, and the bus is proven idle before any actuator power is applied — and actuator power is removed before logic power is removed.
• Motor power never flows through the PMOD connector anywhere in this line; this module has no power terminal at all, so any external voltage on J2 beyond the RS-485 common-mode range (−7 V to +12 V per the datasheet) is a fault condition, not an operating mode.
• The MAX3485 is not isolated. Do not connect the bus between nodes on different mains-referenced supplies without reviewing ground potential difference first. Connect an earth-referenced oscilloscope ground only to module GND.
• A working two-node byte exchange is not EMC, surge, or safety qualification of a field bus. Cable class, shielding, and transient protection (there is no TVS on this board) remain open items.

3. Signal flow and direction-control sequence#

1. At power-up, R2 (10 kΩ) holds DE low: the driver is off and the node cannot disturb the bus even with an unconfigured FPGA. With JP1 bridged, ~RE follows DE low, so the receiver is enabled — the default state is "listen".
2. The FPGA transmits by raising DE (PMOD pin 1), waiting for the driver enable time (datasheet max 90 ns — negligible at UART rates), then shifting the frame out on TXD/DI. With JP1 bridged, ~RE goes high with DE, muting RO so the node does not hear its own transmission (no local echo).
3. Driving DI low forces A low and B high (differential '0'/space); DI high forces A high and B low (differential '1'/mark). Idle mark therefore holds A−B positive while the driver is enabled.
4. After the final stop bit has fully left the shift register, the FPGA drops DE. The driver releases the bus within the datasheet disable time (80–90 ns max), and ~RE returns low, re-enabling the receiver for the reply.
5. With the bus undriven, the idle differential voltage is whatever the termination/bias jumper configuration produces (Section 4.2). With fail-safe bias fitted at exactly one node, A−B idles above +200 mV and every receiver outputs a clean '1' (UART idle).

Why DE turnaround timing is the whole lesson#

The transceiver's own enable/disable times are tens of nanoseconds; the timing that matters is firmware-scale. If the FPGA drops DE before the last stop bit completes, the frame is truncated. If it holds DE too long after the stop bit, the driver is still clamping the bus when the remote node starts its reply — two enabled drivers fight (the datasheet limits driver short-circuit current to ±250 mA, so this is survivable but corrupts every overlapped bit). The correct sequence is: assert DE, transmit, count bit times through the final stop bit, then release DE within about one bit time. At 115200 baud one bit is 8.68 µs, so there is enormous margin over the 90 ns silicon — every turnaround failure on this board will be an HDL bug, and the scope capture of the dead time between DE falling and the reply's start bit is the deliverable that proves the controller correct.

The JP2/shutdown trap#

If JP1 is cut and JP2 bridged (~RE driven from PMOD pin 4), the combination ~RE high with DE low puts the MAX3485 into low-power shutdown after about 300 ns. Recovery is slow by this part's standards: 650–900 ns to re-enable the driver and 720–1400 ns to re-enable the receiver (datasheet tPSL/tPSH, tPRSL/tPRSH). Irrelevant at UART rates, but an HDL that toggles ~RE carelessly will see the first microsecond of traffic disappear. With JP1 bridged (default), DE and ~RE move together and shutdown is unreachable.

4. Interfaces and jumper configuration#

4.1 Connectors#

The map uses PMOD spec 1.2.0 Type 3 (UART) positions: TXD/RXD in the standard slots, DE in the pin-1 CTS slot, ~RE override in the pin-4 RTS slot. RXD is transceiver-driven through R1 per the line rule.

4.2 Termination/bias jumper matrix#

All values assume VCC = 3.3 V, R3 = 120 Ω, R4 = R5 = 390 Ω, receiver input resistance ≥ 12 kΩ (datasheet minimum), and an otherwise idle (undriven) bus. "Far termination" means a second 120 Ω at the other physical bus end. Measure A−B differentially at J2.

Rules restated from the design: terminate at the two physical bus ends only; bias at exactly one node per bus. The MAX3485's built-in fail-safe guarantees RO = '1' only for open inputs; an idle terminated bus sits at 0 V differential — inside the receiver's undefined band — and needs the external bias pair. That is why JP4/JP5 exist.

4.3 Receiver-enable jumpers#

5. Component-by-component review#

Every reference designator in the generated schematic is listed. #FLG01 and #FLG02 are ERC power flags on 3V3 and GND — schematic artifacts with no physical part.

5.1 Transceiver and connectors#

5.2 Line conditioning and defaults#

5.3 Configuration jumpers (all DNP-in-BOM solder jumpers)#

6. Datasheet summary and design interpretation#

Source: MAX3483–MAX3491 family datasheet (Analog Devices/Maxim, doc 19-0333), also mirrored at Farnell; product page: analog.com/en/products/max3485.html. The copy reviewed for this document is Rev 0 (12/94); check the latest revision before procurement.

Design-fidelity note: the family overview (../README.md) catalogs #11 as an "SN65HVD-class" transceiver; the implemented design is a MAX3485. The roles are equivalent (3.3 V half-duplex RS-485) but the catalog line should be corrected to match the schematic.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Confirm U1 pin-1 orientation (SOIC-8: 1 RO, 2 ~RE, 3 DE, 4 DI, 5 GND, 6 A, 7 B, 8 VCC) and the exact suffix MAX3485ESA+ (−40 to +85 °C).
• Verify the PMOD plug pinout against the host board: pins 5/11 GND, 6/12 3V3, and that pin 1 lands on DE, not TXD.
• Measure R1, R2, R3, R4, R5 values before power; confirm C1 present at U1.
• Audit jumper state against the intended bus role: JP1 bridged, JP2 open (default); JP3 per bus position; JP4/JP5 both-or-neither, one node per bus. Record the audit in the bench record.
• Confirm J2 labeling: terminal 1 = A (non-inverting), 2 = B (inverting), 3 = GND. A/B naming conventions differ between vendors; this board follows the MAX3485 datasheet (A non-inverting).
• When layout exists: C1 adjacent to pin 8, short A/B stubs from U1 to J2, solid ground between PMOD and J2 pin 3, jumpers accessible after assembly.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, jumper audit, equipment IDs, and raw scope captures with every step.

Two bench contexts are covered; steps note where they differ.

• Context (a) — PMOD host: module in an FPGA board PMOD socket (AruviX ECP5 or any 3.3 V PMOD host) running the UART + DE turnaround HDL.
• Context (b) — standalone: module powered from a current-limited bench 3.3 V supply on J1 pins 6/12 (3V3) and 5/11 (GND), with a USB-RS485 adapter as the far node and DE/TXD driven by a function generator, GPIO, or jumper wires.

Grounding: in both contexts, run a third wire from J2 pin 3 to the far node's ground. RS-485 tolerates only −7 to +12 V of common-mode offset, and a USB-RS485 adapter's ground is the PC's ground — without the reference wire, the offset between a floating bench supply and the PC is undefined. The scope's earth-referenced ground clip goes to module GND only; measure A−B as two channels with math subtraction (or a differential probe), never by clipping scope ground to B.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist. Photograph the jumper states.
2. Ohmmeter: 3V3-to-GND at J1 — expect no hard short (a reading settling toward high resistance as C1 charges is normal).
3. Ohmmeter at J2 with all of JP3/JP4/JP5 open: A-to-B should read high (receiver input, ≥ 12 kΩ scale), not 120 Ω. Bridge JP3 only if this module is a bus end, then confirm A-to-B ≈ 120 Ω.
4. Verify DE-to-GND ≈ 10 kΩ (R2) and RO-to-RXD ≈ 100 Ω (R1) at the PMOD pads.
5. Confirm JP1/JP2 continuity matches the intended receiver-enable config.

B. First power, no bus#

1. Context (b) first if available: current-limited 3.3 V, no bus wiring, DE and TXD unconnected (R2 idles the node as receiver).
2. Expect supply current ≈ 1–2 mA. Investigate anything above ~5 mA before proceeding.
3. Measure U1 pin 8 = 3.3 V, RXD (PMOD pin 3) = logic high if JP4/JP5 are bridged or the A/B pins are open (open-input fail-safe); if the bus is terminated and unbiased, RXD may be either level or noisy — that is the expected indeterminate case, not a fault, but record it.

C. Driven A/B differential levels#

1. Load the bus with 54 Ω (two 120 Ω bench resistors in parallel across A/B, or JP3 plus a far-end 120 Ω).
2. Drive DE high and hold DI/TXD high (mark): scope A and B vs GND. Expect A high, B low, |A−B| ≥ 1.5 V (typ ≈ 2.4 V), common mode (A+B)/2 within 0–3 V.
3. Hold DI/TXD low (space): expect polarity reversed, same magnitude within ΔVOD ≤ 0.2 V.
4. A differential magnitude well under 1.5 V into 54 Ω means an overloaded bus (too many terminations), a solder fault, or a damaged driver. Stop and isolate before any multi-node work.

D. DE/RE timing and turnaround#

1. Scope channel 1 on DE, channels 2/3 on A and B (math A−B).
2. Toggle DE with DI held high. Measure enable-to-valid-differential (expect ≤ 90 ns) and DE-fall to bus-released — the differential should collapse from the driven level to the jumper-configured idle bias level within ≤ 90 ns plus RC settling of the bias network.
3. Context (a): run the HDL transmitting a frame and capture TXD, DE, and A−B together. Verify DE rises before the start bit, stays high through the entire final stop bit, and falls within about one bit time after it. Measure the dead time from DE fall to the far node's start bit — this capture is the module's turnaround deliverable.
4. If using the JP2 override configuration, additionally verify the node never sits in ~RE-high/DE-low longer than intended, and that receive resumes correctly after shutdown recovery (allow ≥ 1.4 µs).

E. Termination/bias matrix verification#

1. With the bus undriven (all nodes' DE low), step through the applicable rows of the Section 4.2 matrix for this board's role and measure idle A−B with a DMM.
2. Confirm the biased configurations read above +200 mV and that RXD sits at a stable logic '1'.
3. Deliberately record the unbiased-terminated case: idle A−B ≈ 0 V, and observe RXD chatter with a scope while tapping the bus cable — the fail-safe lesson, demonstrated.
4. De-energize before changing any jumper (family rule: no live rewiring).

F. Two-node exchange#

1. Nodes: two AXA-011 modules, or one module (context a) plus a USB-RS485 adapter (context b far node). Wire A-A, B-B, GND-GND. Termination at the two ends; bias at exactly one node.
2. With every remote actuator rail unpowered (family rule), exchange a known byte pattern (e.g. 0x55, 0xAA, incrementing counter) in both directions at 115200 baud, 8N1, at least 10,000 bytes each way.
3. Pass: zero framing/parity errors, zero lost bytes, and no local echo in the JP1 default configuration (a received copy of your own transmission means ~RE is not muting — check JP1).
4. Then half-duplex request/response: master polls, slave answers; scope the bus at the turnaround boundary for driver overlap (a brief contention artifact between the master's release and the slave's start bit indicates an HDL DE-timing bug on one side).
5. Only after this passes: energize actuator rails on downstream nodes one at a time, logic rails first, and re-verify the exchange.

G. Deferred/release-only tests#

Long-cable runs (100 m class), maximum-node loading toward the 32-node limit, data rates above UART class, common-mode stress toward the −7/+12 V limits, and any EMC or surge work are out of scope for first bring-up and need their own plans. The double-termination bias margin (Section 4.2) must be resolved before a multi-drop deployment is declared released.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is minimal and coherent: one transceiver, one decoupling capacitor, defaults that fail safe (R2 idles the node as listener; JP1 makes turnaround a one-pin operation and locks out the shutdown mode), and solder-jumpered termination/bias so a single board serves every bus position — which is exactly the multi-drop lesson the module exists to teach. The datasheet supports every operating assumption: 3.3 V PMOD supply, milliamp-class load, and timing margins thousands of times wider than UART bit periods, which correctly moves the entire turnaround problem into the FPGA HDL where the curriculum wants it.

Open findings, in order of importance:

1. Nothing is fabricated. No board, no HDL, no measurement. This guide is prospective; layout and a DRC-clean fab package now exist, but no physical board has been built or probed.
2. RESOLVED — bias respun from 560 Ω to 390 Ω. The original 560 Ω pair gave only ≈168 mV idle differential against double termination (A−B sees 120 Ω ‖ 120 Ω = 60 Ω), below the ±200 mV worst-case receiver threshold, so RO was undefined on an idle bus. R4/R5 are now 390 Ω 1%, giving ≈236 mV in that worst case — above spec with margin, and still ≈3.6 mA of bias current and a ≈55 Ω driver load (above the 54 Ω RS-485 minimum). Verify the 236 mV figure on the bench before declaring a fully terminated multi-drop bus supported.
3. No transient protection on A/B. Absolute maximum −7.5/+12.5 V, no TVS, on a bus that shares cable runs with actuator wiring in this product line. Acceptable for a bench curriculum board; a finding for anything field-deployed.
4. Catalog mismatch: ../README.md lists #11 as SN65HVD-class; the design is a MAX3485. Correct the catalog.
5. J2 MPN is TBD in the schematic and the datasheet revision reviewed is Rev 0 (12/94); confirm the current ADI revision and ESD rating before procurement.