← AXA-010

Circuit review & bench-test guide

AXA-010 — CAN bus node PMOD module

Document purpose#

This document explains the axa-010-can PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the actuator-line family rules in ../README.md.

This board is an unfabricated prototype design. Status on record: schematic generated, ERC clean (0/0), netlist reviewed; PCB layout has not started, no board has been built, and there is no bench evidence of any kind. Every voltage, resistance, current, and timing value below is a design target derived from the schematic and the MCP2542WFD datasheet — a prediction to verify on the first article, not proof that an assembled board works or is safe.

1. What the board does#

The board is a CAN FD bus physical-layer node with deliberately no CAN controller silicon. A Microchip MCP2542WFD transceiver converts a single-ended TXD/RXD pair from the PMOD host into the differential CANH/CANL bus signals and back. Bit stuffing, CRC-15, arbitration, ACK slots, and error frames are all implemented in FPGA fabric (the can_ctrl core) — that is the L4 lesson of catalog entry #10.

The WFD variant was chosen for its VIO pin: the logic interface (TXD, RXD, STBY) runs at the PMOD's 3.3 V while the transceiver core (VDD) runs from an external 5 V screw terminal, per the actuator-line rule that load/bus power never flows through the PMOD connector. Split termination (two 60.4 Ω halves plus a 4.7 nF common-mode capacitor) sits behind two solder jumpers, bridged by default, so the module can be either a terminating end node or an unterminated stub node.

The module moves nothing itself. But it is a command channel for boards that do — see Section 2.

Functional block diagram#

PMOD host (FPGA, 3.3 V logic)                      external 5 V supply
        |                                                  |
        v                                                  v
   J1 PMOD plug                                    J2 screw terminal
   1 STBY  ── R2 10k pull-down ──┐                 V5_CAN (4.5–5.5 V)
   2 TXD ────────────────────────┤                     │  ├─ C2 100 nF
   3 RXD ◄── R1 100R ── CAN_RXD ─┤                     │  └─ C4 10 µF
   6/12 3V3 ── C3 100 nF ────────┤                     │
   5/11 GND ─────────────────────┤                     │
                                 v                     v
                        ┌──────────────────────────────────┐
                        │      U1 MCP2542WFD (DFN-8)       │
                        │  VIO = 3V3      VDD = V5_CAN     │
                        │  TXD/RXD/STBY   CANH / CANL      │
                        └───────┬──────────────┬───────────┘
                              CANH           CANL
                                │              │
                          JP1 (bridged)  JP2 (bridged)
                                │              │
                             CANH_T         CANL_T
                                └─ R3 60.4R ─┬─ R4 60.4R ─┘
                                          TSPLIT
                                             │
                                        C1 4.7 nF
                                             │
                                            GND
                                │              │
                                v              v
                        J3 bus terminal: 1 CANH, 2 CANL, 3 GND

2. Safety and scope boundaries (actuator-line rules, adapted)#

This is a communications board, not a motor driver: no motor current flows through it and it has no power stage of its own. That does not make it safety-neutral. A CAN bus carries start, stop, speed, and position commands to actuator nodes. A wiring fault, a wrong termination, a stuck-dominant transceiver, or a misframed message from an immature fabric controller can start an actuator on another node — or prevent the frame that stops it. Treat the bus as part of the machine.

• Verify bus behavior with NO actuator power applied anywhere first. Bring up the CAN link — termination, dominant/recessive levels, two-node frame exchange — with every motor/servo/solenoid rail on every connected node unpowered or disconnected. Only energize actuator rails after the bus is demonstrably correct.
• Current-limited first power. First energization of V5_CAN uses a bench supply set to 5.0 V with the current limit at roughly 100 mA. Normal-mode recessive draw is a few mA; dominant transmission peaks near 70 mA worst-case, so 100 mA passes normal operation but catches a solder short.
• Never rewire the bus while any node is driving an actuator. Hot- plugging CANH/CANL can glitch the bus into dominant states and corrupt or fabricate frames. Stop all motion, then change wiring.
• Family rail sequencing on every connected node: logic before actuator rails. On this module that means PMOD 3.3 V (VIO) and the J2 5 V (VDD) come up before any actuator rail anywhere on the bus, and actuator rails go down first. Note the MCP2542WFD has POR on both VDD and VIO and holds CANH/CANL high-impedance until both are valid, and it will not enter Normal mode until TXD is high — so either supply order is safe for the transceiver; the rule exists for the actuators it commands.
• Grounds join at the module (family rule). J2 pin 2 and J3 pin 3 tie to PMOD GND on the board. On the bench, the bus GND reference at J3 must be common with every other node's transceiver ground; the MCP2542WFD receiver tolerates roughly −12 V to +12 V common mode, but do not rely on that margin — run the J3 GND wire alongside the pair.
• An FPGA can_ctrl core under development can hold TXD dominant indefinitely by mistake. The transceiver's TXD permanent-dominant timeout (0.8–5 ms) releases the bus, but other nodes will have seen error frames. Never debug a half-working controller on a bus that also carries live actuator traffic.
• A working two-node frame exchange is not ISO 11898 conformance, EMC, or automotive qualification. This is a teaching prototype.

3. Power and control behavior#

1. With nothing connected, U1 is unpowered; CANH and CANL are specified to disconnect from the bus (high impedance), so an unpowered module does not load a live bus.
2. PMOD attach supplies 3.3 V to VIO (and the module's logic nets). J2 supplies 4.5–5.5 V to VDD. Both PORs must clear; the device then waits for TXD high before entering Normal mode, which prevents it from driving the bus while the host FPGA is still configuring.
3. R2 (10 kΩ) pulls STBY to GND, overriding the chip's internal MOS pull-up to VIO (typically 1.1 MΩ at 3.3 V), so the default state is Normal mode. STBY high = Standby: transmitter off, high-speed receiver off, only the low-power wake receiver active, bus biased to ground.
4. In Normal mode the bus idles Recessive: both CANH and CANL biased to VDD/2 (about 2.5 V), differential about 0 V. Driving TXD low produces Dominant: CANH rises toward 3.5 V typical, CANL falls toward 1.5 V typical, differential 2.0 V typical into a 60 Ω load.
5. RXD mirrors the bus (high = Recessive, low = Dominant), is driven at VIO levels, and reaches the PMOD through R1 (100 Ω series protection).
6. JP1/JP2 bridged (default) place R3 + R4 = 120.8 Ω differential termination across the bus at this node, with C1 grounding the midpoint for common-mode filtering. Cutting both jumpers makes a stub node.

Why split termination behind jumpers#

A CAN bus is terminated only at its two physical ends. A module that is sometimes an end node and sometimes a mid-bus stub needs selectable termination; solder jumpers make the choice deliberate and visible. The split (two 60.4 Ω halves with the midpoint AC-grounded through 4.7 nF) gives the same 120 Ω differential load as a single resistor while shunting common-mode noise at the bias midpoint. Cutting only one jumper is a defect state: it leaves a dangling 60.4 Ω + 4.7 nF single-ended load on one line, unbalancing the pair — always cut or bridge both.

4. Interfaces#

No test points are defined in rev 0.1. For layout (not started), TSPLIT, CAN_RXD, STBY, and V5_CAN deserve probe access; until then, probe at J3, J1, and component pads.

5. Component-by-component review#

5.1 Transceiver and connectors#

5.2 Termination network#

5.3 Logic-side support#

6. Datasheet summary and design interpretation#

All numbers below were read from the Microchip datasheet DS20005514C (MCP2542FD/4FD, MCP2542WFD/4WFD, 2016–2020): MCP2542FD-MCP2542WFD-4WFD-Data-Sheet-DS20005514C.pdf, product page microchip.com/en-us/product/mcp2542wfd. The generator script references the same document at ww1.microchip.com/downloads/en/DeviceDoc/MCP2542FD-4FD-2542WFD-4WFD-Data-Sheet-DS20005514C.pdf. Check the latest revision before procurement. Conditions for the table: VDD = 4.5–5.5 V, VIO = 1.7–5.5 V, RL = 60 Ω unless stated.

Values not confirmed in this review and to be checked directly against the datasheet before stress testing: absolute-maximum VDD/VIO ratings and any reverse-supply rating (the extraction above did not capture the supply-pin absolute-max lines; do not assume). The MPNs for J2/J3 are still "TBD" in the schematic and must be resolved before a BOM is released.

7. Expected values before bench testing#

All values assume VDD = 5.0 V, VIO = 3.3 V, 25 C, and this node terminated (JP1/JP2 bridged) unless stated.

8. Manual schematic and assembly review checklist#

Items 1–3 apply now (schematic stage); the rest on the first article.

1. Confirm the ordered part is MCP2542WFD-E/MF exactly: the MCP2544 variants have no VIO pin and the non-W variant has different wake behavior. The schematic uses the DFN (xMF) footprint; the catalog sketch named the SOIC /SN — the substitution is documented in the README, but the purchase order must match the footprint.
2. Resolve the TBD MPNs on J2 and J3 before BOM release.
3. Layout requirements to carry forward (layout not started): C2/C3 within a few mm of U1; exposed pad stitched to GND per the datasheet recommendation; CANH/CANL short and symmetric (README already requires this); TSPLIT probe access.
4. On the assembled board: verify U1 pin-1 orientation on the DFN and inspect the exposed-pad solder (X-ray or side-view wetting check where available).
5. Verify JP1 and JP2 are in the same state, and that the state matches the node's position on the bus (end = bridged, stub = both cut).
6. Measure R1, R2, R3, R4 in circuit before first power; R3 + R4 should read about 120.8 Ω across J3.1–J3.2 with jumpers bridged.
7. Confirm no continuity between V5_CAN and 3V3 (the two supplies meet only inside U1 and must never be shorted to each other).
8. Buzz the PMOD pin map against the table in Section 4 — especially that pin 2 (TXD) goes to U1 TXD and pin 3 (RXD) comes from R1, not the reverse.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, supply and instrument IDs, ambient, and operator with every capture.

Two bench contexts are covered. Context A (PMOD host): the module plugs into the AruviX ECP5 (or any PMOD host); 3.3 V and grounding come from the host, J2 still needs its own 5 V. Context B (standalone): a bench 3.3 V supply feeds J1 pins 6/12 (3V3) and 5/11 (GND), a signal generator or GPIO adapter drives TXD/STBY, and a USB-CAN adapter is the second node. In both contexts every ground — PMOD GND, J2 GND, J3 GND, the second node's transceiver ground, and the scope reference — must be one common net. A USB-CAN adapter grounds its bus side through the PC and its USB shield; verify with a DMM that its CAN GND really is common with the module's GND before connecting CANH/CANL, and connect the J3 GND wire between nodes, not just the pair.

A. Unpowered inspection and resistance tests#

1. Complete checklist items 4–8 above.
2. Measure J3.1–J3.2 (CANH–CANL): about 120.8 Ω with jumpers bridged.
3. Measure CANH-to-GND and CANL-to-GND: each should read high (through the split, DC path to GND is blocked by C1; expect >100 kΩ after C1 charges, in both meter polarities). A reading near 60 Ω here means C1 is shorted — see Section 5.2.
4. Measure V5_CAN-to-GND and 3V3-to-GND resistance in both polarities; investigate any hard short. Confirm no continuity V5_CAN to 3V3.

B. First power, no bus#

1. Context A: attach the PMOD host but leave the FPGA unconfigured (pins Hi-Z; U1's internal 33 kΩ TXD pull-up keeps the bus recessive). Context B: apply bench 3.3 V, current-limited to 100 mA, TXD input left open.
2. Apply 5.0 V to J2, current-limited to 100 mA. Expect a few mA.
3. Verify recessive idle: CANH and CANL both near 2.5 V, differential within −500 to +50 mV, RXD (J1.3) high at 3.3 V, STBY node under 0.3 V.
4. Abnormal here: both lines near 0 V suggests standby (check STBY and R2) or a VDD/VIO POR problem; a large differential suggests a stuck driver.

C. Termination verification (board-specific)#

1. Unpowered, one node: J3.1–J3.2 reads about 120 Ω (done in step A.2).
2. Connect the second node (USB-CAN adapter with its terminator enabled, or a second module with jumpers bridged), all power off: the same measurement now reads about 60 Ω. If it still reads 120 Ω, the second node is unterminated; if about 40 Ω, there are three terminators on the bus.
3. C1 check under power: with the bus idle, TSPLIT (junction of R3/R4) should sit near the 2.5 V recessive bias. Near 0 V with correct line voltages is impossible; lines dragged low with TSPLIT at 0 V means C1 is shorted.
4. Reflection demonstration (optional, needs several meters of cable to be visible): transmit at 500 kbit/s or above over 5–10 m of twisted pair and capture a dominant-to-recessive edge with both end terminators in place; then remove the far terminator and capture again. Expect visibly slower, stepped, or ringing recessive edges — the recessive state is only driven by the termination, so it degrades first. On a short bench loop the difference may not be demonstrable; say so in the record rather than forcing a conclusion.

D. Single-node transmit and the ACK trap (board-specific)#

1. One powered node only, terminated, no second node. Drive TXD from the host with a slow square wave (for example 10 kHz) — raw bit-banging, no CAN framing needed.
2. Scope CANH (ch1), CANL (ch2), and the math difference. Expect per Section 7: recessive both about 2.5 V / diff about 0 V; dominant CANH about 3.5 V, CANL about 1.5 V, diff 1.5–3.0 V. Verify RXD echoes TXD with under about 120 ns plus wiring delay.
3. Hold TXD low continuously: the bus must go recessive again within 0.8–5 ms (tPDT). This proves the stuck-controller protection.
4. The classic bring-up trap: once real CAN frames are transmitted, a single node on the bus will never see an ACK — CAN requires some other node to drive the ACK slot dominant. A lone can_ctrl core will report ACK errors, retransmit endlessly, and eventually go error-passive. This is correct protocol behavior, not a board fault. Do not debug the transceiver for it; add the second node first.

E. Two-node frame exchange (smoke test)#

1. Connect the second node (USB-CAN adapter in Context B, or a second AXA-010 on a second PMOD/host). Confirm 60 Ω across the bus unpowered, common ground verified, no actuator power anywhere on the bus.
2. Power both nodes. Send a single frame from the adapter at 500 kbit/s (classic CAN first; CAN FD and higher rates only after classic works).
3. Verify on the scope that the module's RXD reproduces the frame, and that during the ACK slot the module's controller (once implemented) drives one dominant bit — visible as a dominant bit the adapter did not send. Until can_ctrl exists, the adapter alone will show its own ACK-error/retransmit behavior, mirroring step D.4.
4. Transmit from the module; verify the adapter receives the intended ID and payload and that the frame is ACKed (no retransmission storm).
5. Only after sustained, error-free exchange in both directions may this bus be connected to nodes with actuator rails, and then per Section 2.

F. STBY and wake verification (board-specific)#

1. Bus idle, two nodes powered. Measure V5_CAN current: a few mA (normal).
2. Drive STBY (J1.1) high. Expect: VDD current drops to the microamp range (4 µA typ / 16 µA max total); CANH and CANL fall from about 2.5 V to ground bias (within ±0.1 V); RXD stays high.
3. Drive TXD while in standby: nothing may appear on the bus — the transmitter is off. Any bus activity here means STBY is not actually reaching U1 (check J1.1 wiring and R2).
4. Wake test: have the second node transmit a frame. A normal frame contains dominant/recessive/dominant phases satisfying the WUP filter (each phase at least 0.5–3.6 µs — at 500 kbit/s a 2 µs bit qualifies marginally; use 125–250 kbit/s for a robust wake stimulus). RXD must fall on wake. Note: the transceiver does not resume transmitting by itself; the host must release STBY (normal mode within 7–30 µs).
5. Release STBY and confirm current and bus bias return to normal.

G. Not covered on this bench#

ISO 11898-2 conformance, EMC (a common-mode choke is suggested by the datasheet above 1 Mbps and is not on this board), bus faults to battery voltages, 8 Mbps CAN FD signal integrity, and temperature range all require a controlled lab plan and are out of scope for first bring-up.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is small and coherent: one transceiver, correctly split supplies (VDD from a dedicated screw terminal, VIO from the PMOD 3.3 V), a deliberately defaulted STBY pull-down whose polarity was checked against the datasheet, jumpered split termination, and the family's series-protection and grounding rules applied. The datasheet review supports every claim made in the schematic notes, including the STBY polarity and the WUP wake behavior specific to the W variant.

The principal open risks are: no layout exists, and the decoupling placement, H/L symmetry, and exposed-pad grounding requirements live only in this document and the README until it does; two connector MPNs are TBD; the absolute-maximum supply ratings were not confirmed in this review and must be read from the datasheet before any overvoltage or reverse test; the 0603 termination resistors are not rated for automotive-style bus faults; and the module's real purpose — hosting a fabric CAN controller — cannot be exercised until the can_ctrl core exists, at which point the single-node-ACK trap and the stuck-dominant timeout in Section 9 become the first things its testbench and bring-up plan must reproduce. Above all: this board commands boards that move. The no-actuator-power-first rule in Section 2 is the one line in this document that must never be skipped.