← AXA-007

Circuit review & bench-test guide

AXA-007 — STSPIN230 BLDC/FOC driver dual-PMOD module

Document purpose#

This document explains the axa-007-bldc dual-PMOD BLDC/FOC driver module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, the actuator-line overview (../README.md), and the manufacturer datasheets cited in section 7.

This board is an unfabricated prototype design. Status at time of writing: schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, no board built, no bench evidence of any kind. Every number below is a design target or a datasheet figure to verify, not proof that an assembled board is safe or functional. Several values are still marked TBD in the schematic (shunt MPN, both screw-terminal MPNs, the hall socket MPN). The module is marked NOT RELEASED; the design-review checklist and DRC gates have not run.

1. What the board does#

AXA-007 is the actuator line's flagship: a three-phase BLDC driver module that puts the entire control loop — commutation, dead time, current sensing, and eventually field-oriented control — in FPGA fabric. There is no MCU and no smart gate driver making decisions: the STSPIN230 is a protected triple half-bridge power stage with six direct gate inputs (INxH/INxL per half-bridge), so the host fabric owns commutation AND dead time. A single low-side shunt feeds an INA240A1 current-sense amplifier (chosen for its enhanced PWM rejection) into an ADS7042 12-bit 1 MSPS SPI ADC, closing the current loop back through PMOD B. A five-pin hall socket provides rotor position for six-step and hall-FOC operation; the sensorless back-EMF observer is a later curriculum step that keeps the hall socket as truth reference.

The module spans two adjacent host PMOD connectors (0.9 inch centers). Motor power (VM, 1.8-10 V) enters only through the J2 screw terminal, never through the PMOD — the line's one hard rule. The PMODs carry 3.3 V logic only.

Functional block diagram#

HOST FPGA (dual PMOD)                         MODULE                    MOTOR
                                 ┌──────────────────────────────┐
J1 PMOD A "DRIVE" ──────────────>│                              │
  1 INUH  2 INVH  3 INWH         │  U1 STSPIN230                │
  7 INUL  8 INVL  9 INWL ───────>│  triple half-bridge          │── OUTU ─┐
  4 EN/nFAULT <──(R2/R1 10k pu)─>│  1.8-10 V, 1.3 A rms         │── OUTV ─┼─> J4
  10 STBY ──(R3 10k pd)─────────>│  interlock + 50 ns typ DT    │── OUTW ─┘  (BLDC)
  5,11 GND  6,12 3V3 ───────────>│  OC 2 A typ, TSD 160 C       │
                                 │       │ SENSE (pins 4+9)     │
J2 screw terminal ── VM 1.8-10V >│  C1,C2 10uF + C3 100nF       │
                     GND ───────>│       │                      │
                                 │  R10 0.05R 2512 shunt        │
                                 │       │ (50 mV/A)            │
J3 PMOD B "SENSE" <──────────────│  U2 INA240A1 x20             │
  1 ~CS  3 MISO(R13)  4 SCK <───>│   REF1+REF2 = VREF_MID       │
  7 HALL1 8 HALL2 9 HALL3 <──────│   (R11/R12 10k/10k = 1.65 V) │
  5,11 GND  6,12 3V3 ───────────>│       │ 1 V/A about 1.65 V   │
                                 │  U3 ADS7042 12-bit 1 MSPS    │
                                 │                              │
J5 hall socket (3V3/GND/H1-3) <──│  R4-R6 10k pullups,          │<─ hall PCB
                                 │  R7-R9 100R series           │   on motor
                                 └──────────────────────────────┘

PMOD A carries the six timing-critical gate inputs plus EN/nFAULT and STBY. PMOD B carries the ADC SPI (Type-2 SPI positions: ~CS/MISO/SCK, no MOSI — the ADS7042 has no data-in pin) plus the three hall signals on pins 7-9.

2. Safety and scope boundaries — actuator-specific#

A BLDC motor is not a resistor. It spins fast, stores rotational energy, and acts as a generator whenever the shaft turns. The following rules are mandatory for all bring-up work on this module.

2.1 GIMBAL-MOTOR-ONLY rule for bring-up#

• Use only a small, high-resistance gimbal-class BLDC for all first tests: phase resistance roughly 5-15 ohm, so that even a hard commutation error or a stalled rotor draws well under ~1 A from a low VM. This matches the STSPIN230's 1.3 A rms / 2 A typical overcurrent envelope.
• Never use a low-resistance drone/hobby ESC motor for bring-up. Sub-ohm windings draw tens of amps at stall or on a commutation error — far beyond the STSPIN230, the 0.05 ohm shunt's thermal budget, and any 20 x 40 mm 2-layer module. The 1.8-10 V rating does not make a 2205-class racing motor safe on this board.
• First power is always through a current-limited bench supply on VM (start at 50-100 mA limit, raise deliberately and record each step).

2.2 Stored energy, generation, and regeneration#

• A spinning BLDC is a generator. Never disconnect a phase lead (J4) while the motor is spinning or while VM is applied. Breaking an inductive, generating circuit arcs across the screw terminal and can avalanche the bridge. Stop the motor, remove VM, wait, then touch the wiring.
• A decelerating motor pumps energy back into VM through the STSPIN230's integrated body diodes (VDF about 0.9 V at 1.3 A per the datasheet). The on-board reservoir is only 2 x 10 uF + 100 nF. A bench supply that cannot sink current may overvolt on regeneration — VS absolute maximum is 11 V, so at VM = 10 V there is almost no headroom. For any test involving deceleration or external back-driving of the shaft, either keep VM at or below ~5-6 V, add an external bulk capacitor/dissipative clamp at J2, or use a two-quadrant supply. Record the VM waveform during the first deceleration.
• Do not hand-spin the shaft rapidly with the module connected and VM absent: the generated phase voltage back-feeds VS through the body diodes and can power the module unexpectedly.

2.3 Rail sequencing#

• Logic 3.3 V before VM, always. With 3.3 V absent, the gate inputs float at the module (the FPGA side is undefined) while R3 holds STBY low; standby keeps the power stage in high impedance, which is the designed safe state — but do not rely on it as the only barrier. Apply 3.3 V, confirm STBY low and EN behavior, then apply VM.
• Remove in reverse order: VM off first (motor stopped), then 3.3 V.

2.4 Mechanical safety#

• Hands clear before enable. No fingers, hair, sleeves, probe leads, or loose cables anywhere near the rotor before STBY is driven high. Adopt this as a spoken bench convention ("clear") before every enable.
• Secure the motor body before first spin. Clamp or bolt it to the bench. Commutation errors cause violent torque steps and the reaction torque will throw an unsecured motor. Remove any propeller, gear, or load from the shaft for all bring-up work.
• Safety glasses for first spin and for all overcurrent/fault-injection tests.

2.5 Scope boundaries#

• VM absolute maximum is 11 V and logic inputs 5.5 V; never connect a 12 V supply to J2, even briefly.
• This guide covers module bring-up only. Motor parameter identification, FOC tuning, and sensorless operation are HDL curriculum items with their own verification story (section 8).
• A working spin is not EMC, safety, or reliability qualification.

3. Power and control sequence#

1. With no supplies, R3 (10 k) plus the STSPIN230's internal ~36 k pull-down hold STBY low: the device is in standby, power stage high-impedance, consumption below 80 nA per the datasheet.
2. Logic 3.3 V arrives via the PMOD (or bench supply). R1 (10 k) pulls EN/nFAULT toward 3.3 V; the STSPIN230's internal 10.5 uA typical EN pull-down leaves the node near 3.2 V. R11/R12 establish VREF_MID = 1.65 V; U2 and U3 power up. The ADS7042 requires an offset-calibration frame after power-up (section 7) before codes are trustworthy.
3. VM arrives at J2. The STSPIN230 UVLO releases as VS rises through 1.45-1.79 V; the outputs stay high-impedance because STBY is still low.
4. The host drives STBY (J1 pin 10) high (>= 1.48 V required). Leaving standby resets the control logic to power-up state.
5. The host releases or drives EN/nFAULT high and applies INxH/INxL patterns. Per the datasheet truth table: INxH=1/INxL=0 turns the high side on, INxH=0/INxL=1 turns the low side on, 0/0 and 1/1 are both high-impedance (1/1 is the interlock case), and EN=0 forces all bridges high-impedance.
6. Bridge return current flows through the paralleled SENSE pins (4 and 9, which the datasheet requires to be tied together) into shunt R10. 50 mV/A x 20 V/V = 1 V/A appears at INA_OUT, centered on 1.65 V; U3 digitizes it on demand over the J3 SPI.
7. On overcurrent (2 A typical), short circuit, or thermal shutdown (160 C typical, 40 C hysteresis) the STSPIN230 disables the power stage and yanks EN/nFAULT low through its internal open-drain MOSFET. Review finding: this board populates only the R1 pull-up — there is no CEN capacitor, so the datasheet's REN/CEN disable-time network is absent and the automatic retry after a fault is nearly immediate. The fabric MUST latch any nFAULT-low event and hold the bridge off itself; do not rely on the chip's retry timing for protection of the motor or wiring.

4. Connectors, pin maps, and both bench contexts#

Bench context (a): dual-PMOD FPGA host#

Both plugs seat into two adjacent host PMODs on 0.9 inch centers (verify the host's connector pitch against PMOD spec 1.2.0 before layout sign-off). The host supplies 3.3 V and ground on pins 5/6/11/12 of both connectors; confirm the host's 3.3 V budget covers the module (a few mA) plus whatever the hall board draws from J5. VM comes from a separate current-limited bench supply into J2. Grounding: logic ground (PMOD) and motor ground (J2) join on the module; do not add a second external bond between the VM supply negative and the host ground, or motor return current will find the PMOD ground pins. Scope grounds go to the module GND (J2 pin 2 or a PMOD GND pin), and only one earth-referenced ground point in the whole setup.

Bench context (b): standalone logic supply#

For module-only tests without an FPGA: a bench 3.3 V supply (current limit ~100 mA) feeds pins 6/12 (3V3) and 5/11 (GND) of J1 — J3 shares the same nets through the module, verify with a meter before relying on it. A second, separate current-limited supply feeds VM at J2. Static input levels can be set with clip leads to 3V3/GND (the inputs are ordinary logic inputs; VIH >= 1.6 V, VIL <= 0.6 V). Sequencing is now manual — you are the interlock: 3.3 V first, VM second, and never leave gate inputs floating while VM is up. The two supplies' returns meet only at the module ground. The ADC cannot be read without an SPI master; standalone context covers the analog chain (DC injection, section 10.E) and gate mapping with static levels.

5. Component-by-component review#

Every reference designator in the generated schematic appears below.

5.1 Power stage and connectors#

5.2 Drive-side support network#

5.3 Current-sense chain#

5.4 Hall interface#

5.5 Power flags#

#FLG01/#FLG02/#FLG03 (3V3, GND, VMOT) are ERC power-flag symbols only; they place no physical parts and need no bench action.

6. The mA-per-LSB discrepancy (review finding)#

The schematic note and README state "~1.24 mA/LSB". The correct figures from the chain design values are:

• Chain gain: 0.05 ohm x 20 V/V = 1.00 V/A (nominal), centered on 1.65 V.
• ADS7042 LSB at 3.3 V reference: 3.3 V / 4096 = 0.806 mV.
• Therefore 0.806 mA per LSB, equivalently 1.241 LSB per mA.

The documented "1.24 mA/LSB" appears to be the inverse (1.24 codes/mA) with the units swapped. Nominal conversion, pending calibration (section 10.E):

I_bus [A] = (code - code_zero) x (3.3 / 4096) / (Rshunt x 20)
          = (code - 2048_nominal) x 0.000806   [A, nominal values]

Usable range before INA240 output clipping: roughly -1.6 A to +1.6 A, which brackets the 1.3 A rms motor rating and the 2 A typical OC threshold only marginally — a hard OC event may clip at the amplifier before the ADC sees it.

7. Datasheet summary and design interpretation#

Official references: STSPIN230 product page and STSPIN230 datasheet PDF (DocID029312; figures above read from Rev 2), INA240 product page and INA240 datasheet PDF (SBOS662C), ADS7042 product page and ADS7042 datasheet PDF (SBAS608C), Vishay WSL datasheet. Values not listed above (for example the STSPIN230 Rth(JA), which the datasheet itself marks TBD, and the WSL part's exact TCR) must be checked against the latest datasheet revision before release. Check current revisions and exact orderable suffixes before procurement.

8. Fabric-testbench-first rule (mandatory gate)#

No bitstream touches this board until the commutation logic has passed a self-checking simulation testbench. This is the actuator-line release bar and, for a six-gate bridge, a safety gate. The testbench must prove, at minimum:

• All-off at reset: every INxH/INxL output is 0 (and STBY low, EN released) from reset until explicitly enabled.
• No both-gates-on state, ever: for each phase, INxH AND INxL is never 1 on the same cycle, across all commutation states, state transitions, fault entry/exit, and enable/disable — asserted with a monitor, not eyeballed. (The STSPIN230's 1/1 interlock gives high-Z, not damage, but the fabric must not lean on it.)
• Explicit dead time of a parameterized width (>= 500 ns for bring-up) inserted at every high/low handover, verified by the monitor.
• nFAULT latching: a simulated nFAULT-low pulse forces all outputs off and keeps them off until software/user re-arm (because the board has no CEN disable-time network).
• Hall-input decoding tested against all 6 valid states and both invalid states (000, 111 must not command any drive).

Only after the testbench passes, and after section 10.D confirms the physical mapping, may the same RTL drive the assembled board.

9. Expected values before bench testing#

All values are design targets or datasheet figures — nothing has been measured on hardware.

10. Ordered bench-test procedure#

Stop at the first abnormal result. Record everything against the bench record template (section 12). Sections A-C use bench context (b) or (a); D onward assume a working logic context. No motor is connected until section F is complete.

A. Unpowered inspection and resistance tests#

1. Visual inspection under magnification: U1 orientation and EPAD fillets (X-ray if available), U2/U3 pin-1 orientation, no bridges on the VQFN-16 0.5 mm pitch and the VSSOP-8 0.5 mm pitch, R10 fillets on both ends.
2. Confirm the assembly against the BOM: U2 marked as A1 variant (gain 20), R10 is the 0.05 ohm part (a 0603 10 k reflowed into a 2512 site has happened to better labs).
3. Meter, both polarities: VM-to-GND, 3V3-to-GND, each J4 phase-to-VM and phase-to-GND (expect body-diode signatures one way, high the other), INA_OUT-to-GND, VREF_MID-to-GND (~5 k to 3V3 net via R11/R12 divider).
4. R10 across its pads: at 0.05 ohm this is below most DMM floors — verify it is not open (short-range beep with milliohm caveat) and plan the real value extraction from the DC injection in step E.
5. Buzz J1/J3 pin-to-net continuity: each of the six gate pins to its U1 input pin (J1.1-INUH-U1.2, J1.2-INVH-U1.16, J1.3-INWH-U1.12, J1.7-INUL-U1.1, J1.8-INVL-U1.15, J1.9-INWL-U1.11), J1.4 through R2 to U1.13, J1.10 to U1.14, J3.1/3/4 to U3, J3.7-9 through R7-R9 to J5.
6. Verify J1 and J3 3V3/GND pins are common on the module; verify J5 pin 1 is 3V3 and pin 2 is GND with the meter (this protects the hall board later).

B. Logic-rail first power (no VM, no motor)#

1. Context (b): 3.3 V bench supply, current limit 100 mA, to J1 pins 6/12 and 5/11. Context (a): plug into the host with the FPGA unconfigured.
2. Current draw per section 9. Investigate any excess before proceeding.
3. DMM: VREF_MID (record it — this number feeds the calibration), INA_OUT (should sit at VREF_MID +/- a millivolt), EN/nFAULT node (~3.2 V), STBY (near 0 V), hall pins (~3.3 V with J5 empty).

C. ADC SPI bring-up (no VM)#

1. Context (a) with a minimal SPI-master bitstream (that has passed its own testbench), or a logic analyzer plus any 3.3 V SPI master in context (b).
2. Send the power-up calibration frame: CS low, >= 16 SCLKs, discard the all-low response. Then read continuously.
3. Expect frames of 2 leading zeros + 12 bits; code near mid-scale (record code_zero at zero current). Verify SCLK frequency and that data is stable across many reads (a few LSB of noise is normal; large flicker points at C5/C7/layout or SCLK integrity through R13).

D. Six-gate mapping verification (VM low and current-limited, NO motor)#

The STSPIN230 integrates its gates, so mapping is verified at the phase outputs, not at discrete MOSFET gates — but the principle is identical: prove the mapping before real VM or a motor is ever connected.

1. Motor disconnected from J4. VM bench supply set to 3.0 V, current limit 50 mA, connected to J2. 3.3 V logic already up. STBY high, EN released.
2. Drive exactly one of the six gate signals at a time from the host (or clip leads in context (b)), all others low. Scope on the corresponding J4 pin:

High-impedance pins float; a 10 k resistor to GND on the probed pin makes the high-Z state readable. Any swapped pair (wrong phase responds) or inverted sense (H input pulls the phase low) is a wiring/RTL mapping error: fix it now, not after VM and a motor are attached.

1. Also verify: INxH and INxL both high on one phase gives high-Z (interlock), and EN driven low forces all three phases high-Z regardless of inputs.
2. Verify STBY low puts everything in high-Z and (per datasheet) resets the control logic on wake.

E. Current-chain DC calibration (INA240 + ADS7042)#

Inject a known DC current through the shunt path and calibrate the whole chain end to end.

1. Setup: VM supply disconnected. Inject current into the SENSE/shunt path: set a bench supply to current-limit mode (constant current) at 100 mA with a series resistor (e.g. 10-33 ohm power resistor to keep the CC loop stable), from the U1 SENSE net side of R10 (probe point: the shunt's SNS_P pad) returning to module GND. Alternatively drive one low-side switch on (INxL high, VM at 3 V current-limited, phase pin strapped to VM through a power resistor) so real bridge return current flows — the first method is cleaner, use it if the SNS_P pad is accessible.
2. Verify the true injected current with a DMM in series (do not trust the supply readout).
3. At I = 0: record VREF_MID, INA_OUT, and ADC code (code_zero).
4. At I = +50 mA, +100 mA, +200 mA, +500 mA, +1.0 A (respect the injection resistor's power rating): record INA_OUT and ADC code at each point.
5. Compute effective gain and offset by least squares: code(I) = G_eff x I + code_zero. Nominal G_eff = 1241 codes/A (= 0.806 mA/LSB). Compare the extracted V/A slope at INA_OUT against Rshunt x 20 = 1.00 V/A; disagreement beyond ~1.5% (1% shunt + 0.2% gain error + divider/reference effects) means a wrong part or a measurement problem.
6. If polarity allows, repeat with reversed injection for two or three negative points to confirm bidirectional symmetry around code_zero.
7. Document the resulting ADC-code-to-amps conversion (measured G_eff and code_zero, date, temperature) in the bench record; the fabric current loop uses these numbers, not the nominals.

F. Hall sensor socket check#

1. With J5 empty and logic power on: pin 1 = 3.3 V, pin 2 = 0 V, pins 3-5 pulled to ~3.3 V through R4-R6. Cross-check the hall board's own datasheet/pinout against this order (3V3/GND/H1/H2/H3) before plugging it in — hall breakout boards do not share a standard pinout, and reversed supply kills hall ICs. Confirm the hall outputs are open-collector or push-pull 3.3 V-tolerant, and that 10 k pull-up sink current is within their rating.
2. Plug the hall board in, logic power only. Confirm 3.3 V rail current rises by the hall board's expected draw and no pin sits at an intermediate level.
3. Mount the hall board on (or verify it is integral to) the motor. Rotate the shaft slowly by hand (no VM connected) and scope/log J3 pins 7-9.
4. Verify all three signals toggle, and record the six-state sequence over one electrical revolution in both directions, e.g. 101 - 100 - 110 - 010 - 011 - 001 (CW). Confirm 000 and 111 never occur (if they do: wiring, a dead hall, or wrong hall board). This recorded sequence, together with the phase mapping from step D, defines the commutation table — write it down; do not trust any motor vendor diagram over your own measurement.

G. Dead-time and complementary verification per phase leg#

1. Load the testbench-passed commutation bitstream, but run it in a "static + slow PWM" debug mode. Motor still disconnected; VM 3 V, current-limited.
2. Scope each INxH/INxL pair at the J1 pins (two channels, single trigger): verify complementary drive with the programmed dead time at every edge, for all three phases, at the bring-up PWM frequency. No overlap, ever.
3. Scope the corresponding J4 phase during PWM: the phase should slew between VM and GND with clean high-Z gaps during dead time (body diodes and the floating pin define the shape at no load — record it as a reference).
4. Verify a forced nFAULT (short EN_FLT node to GND briefly through 1 k) kills all six drives and that the fabric latch holds them off.

H. First spin (gimbal motor only) and current loop#

1. Preconditions: sections A-G all pass; motor is a gimbal-class BLDC (section 2.1) bolted down; shaft bare; hands clear; VM supply at 3-5 V with current limit 300 mA; safety glasses on.
2. Six-step commutation from the recorded hall table, low duty (10-20%). Expect slow, smooth rotation. If it twitches or locks: stop, re-check hall order and phase mapping (the two most likely culprits) — do not raise the current limit to "push through" a wrong commutation table.
3. Log ADC current while spinning; sample in the PWM valley as designed. Verify the reading against the VM supply current (bus current at low duty is pulsed — compare averages thoughtfully, not blindly).
4. Raise VM and load in small recorded steps. Watch: VM voltage during deceleration (regeneration, section 2.2), shunt and U1 temperature, and nFAULT. The STSPIN230 has no heatsink beyond the EPAD copper: at 1 A rms and 0.4-0.65 ohm total RDS(on), the package dissipates 0.4-0.65 W — thermal behavior on the not-yet-designed layout is a release question.
5. Only after six-step is boring: hall-FOC, then sensorless, per the curriculum. Each new HDL stage re-enters at step G with its own testbench evidence.

11. Troubleshooting map#

12. Bench record template#

13. Review conclusion#

The architecture is coherent and deliberately educational: a protected integrated power stage (STSPIN230) with six direct inputs pushes commutation and dead-time responsibility into fabric, while the shunt-INA240-ADS7042 chain gives the fabric a real 1 V/A, PWM-rejecting current loop and the hall socket provides ground truth for position. The dual-PMOD split is sensible (all six timing-critical gate lines on one connector) and the default-off conventions (STBY pull-down, interlock truth table, series resistors on every module-driven line) are consistent with the rest of the line.

The principal open risks, in order: the board does not exist (no layout, so Kelvin shunt routing, EPAD thermals, decoupling placement, and the 0.9 inch dual-plug mechanics are all unverified); no CEN network means fault retry is effectively instantaneous and protection depends on the fabric latching nFAULT — this must be treated as a firm RTL requirement, not a suggestion; no reverse-polarity or overvoltage protection on VM against an 11 V absolute maximum, with regeneration able to pump VM upward on deceleration; the documented 1.24 mA/LSB figure is inverted (correct: ~0.81 mA/LSB, 1.24 LSB/mA) and should be fixed in the README and schematic note before it propagates into HDL scaling constants; the STSPIN230's dead time and OC threshold are typical-only figures; and three connector MPNs plus the shunt MPN remain TBD. None of these blocks fabrication, but every one of them must be closed — and this guide's sections A-H executed in order, stopping at the first abnormal result — before the module earns released status.