← AXA-005

Circuit review & bench-test guide

AXA-005 — 8-channel RC servo bank PMOD module

Document purpose#

This document explains the axa-005-servo-bank prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the actuator-line overview in ../README.md.

This board has never been fabricated. Repository status is: schematic generated, ERC clean (0/0), netlist reviewed, PCB laid out, DRC clean (0 violations, 0 unconnected), fab package exported — but not released. There is no physical board and no bench evidence of any kind. Every voltage, current, and timing value below is a design target derived from the schematic and manufacturer datasheets, to be verified on a first article that does not yet exist. Trace widths, copper ratings, and thermal behavior are unknowable until layout is done; where this guide refers to them it states assumptions that layout review must replace with facts.

1. What the board does#

The board is an 8-channel RC servo fan-out PMOD module. A host FPGA (or any 3.3 V PMOD source) drives eight independent PWM lines into a single SN74HCT541 octal buffer. The buffer is deliberately powered from 5 V, not from the PMOD 3.3 V: its TTL-threshold inputs (VIH = 2.0 V) accept the host's 3.3 V CMOS levels while its outputs swing to 5 V. That is the intended 3.3 V-to-5 V level-shift lesson. That 5 V rail (V5BUF) comes from U2, an AP2204K-5.0 LDO fed from VSERVO — the buffer is not wired straight to the servo pack, because the '541's recommended supply tops out at 5.5 V (Section 3.3). Each buffered output passes through a 100 Ω series resistor to one of eight standard SIG/V+/GND servo headers. Servo power enters only on the J3 screw terminal — never through the PMOD. A solder jumper (JP1) grounds the buffer's active-low output enables; cutting it forces all eight signal outputs high-impedance (R17 pulls the enables to V5BUF so the cut state is defined).

There is no PWM generator, no microcontroller, and no PCA9685 on the board — generating eight phase-aligned 50 Hz channels in FPGA fabric is the curriculum point. There is also, in the current revision, no fuse, no polyfuse, no reverse-polarity protection, and no per-channel current limit on VSERVO (an explicitly deferred line decision). The module is a buffer and a power distribution point, nothing more; all rail protection is the bench supply's job until that decision lands.

Functional block diagram#

PMOD host (3.3 V logic)                    external servo supply 5-6 V
        |                                            |
        v                                            v
J1 PMOD plug (Type 1 GPIO)                 J3 screw terminal (VSERVO, GND)
 pins 1-4,7-10 = PWM1..PWM8                          |
 pins 5,11 = GND   pins 6,12 = 3V3 (unused)          +--> C2,C3,C4 3x10uF bulk
        |                                            +--> J4..J11 servo V+
        |                                            |
        |                                            v
        |                                   U2 AP2204K-5.0 LDO
        |                                   (C5 in, C6 out, EN tied to VIN)
        |                                            |
        |                                            v
        |                                     V5BUF (regulated 5 V)
        v                                            +--> C1 100nF at U1
   A1..A8 inputs                                 VCC (V5BUF)
        |                                            |
        +---------------> U1 SN74HCT541 <------------+
                          octal 3-state buffer
   ~OE1/~OE2 <--- OE_N net <--- JP1 (bridged: OE_N=GND, outputs ON)
                              <--- R17 10k to V5BUF (JP1 cut: hi-Z)
                          |
                 Y1..Y8 outputs (swing to V5BUF = 5 V)
                          |
                 R1..R8 100R series, one per channel
                          |
                          v
        J4..J11 servo headers, each: 1 SIG, 2 VSERVO, 3 GND
                          |
                          v
                up to eight RC servos (grounds join on this module)

2. Safety and scope boundaries — actuators move#

This module drives geared actuators. A hobby servo horn develops enough torque to pinch fingers, strike nearby objects, snap its own gears against a hard stop, and drag wiring into itself. The following rules are not optional:

• Hands clear before the first commanded movement. At power-up, or at the instant a valid pulse train first appears, a servo can slam at full speed to the commanded position from wherever its horn happens to be. Treat every first power-up and every firmware load as a potential full-travel slew. Remove horns, or leave the mechanism unloaded and clear, for all bring-up.
• Current-limited first power, always. Set the bench supply current limit low for the first tests (see the ordered procedure) and raise it only as the test plan requires. There is no fuse on this board.
• Stall currents are large. Typical estimates (marked as such — verify against the actual servos used): an SG90-class micro servo stalls at roughly 0.7–1 A; an MG996R-class standard servo stalls at roughly 2–3 A at 6 V. These are typical hobby figures, not datasheet guarantees.
• Servos draw large transients even unloaded. A step command produces a hard acceleration; the motor draws near-stall current for tens of milliseconds. Eight servos given a simultaneous step command transient together. This is why C2–C4 exist and why the supply and wiring matter.
• Never hot-plug or hot-unplug a servo connector while VSERVO is powered. The three pins do not make or break in a controlled order; a momentary SIG-to-V+ or V+-to-GND scrape is possible, and the inductive motor load arcs the contacts. Power down VSERVO, change connectors, power up.
• Rail sequencing: bring the logic side (host 3.3 V / PWM idle-low) up first, then VSERVO; remove VSERVO before the logic side. Reasons and the one datasheet nuance that complicates this are in section 3.
• ONE SERVO FIRST. Bring the board up with a single servo, on one channel, commanded to mid-range (1.5 ms), before ever populating the full bank.
• A working single-servo demo is not a qualification of the 8-channel current path, connector heating, or brown-out behavior. Those are separate tests.
• This is a low-voltage board; the hazards here are mechanical (motion) and thermal (stall heating, undersized contacts), not electrical shock.

3. Power and control sequence#

1. VSERVO from J3 powers U2 (the LDO), the bulk capacitors, and every servo header V+ pin directly. Nothing on the board is powered from the PMOD 3V3 pins; they land only on a schematic power flag.
2. With JP1 bridged (the as-designed default), OE_N is grounded, so U1's ~OE1/~OE2 are both low and all eight buffers drive. With JP1 cut, R17 (10 kΩ to V5BUF) pulls OE_N high and all eight Y outputs are high-impedance — the datasheet function table confirms either enable high forces Z on all outputs.
3. Host PWM (3.3 V CMOS) arrives on A1–A8. HCT input thresholds are VIH ≥ 2.0 V, VIL ≤ 0.8 V, so 3.3 V logic clears the high threshold with 1.3 V of margin.
4. Y1–Y8 reproduce the input logic, swinging to V5BUF (5 V) levels (VOH ≥ 3.84 V at VCC = 4.5 V, −6 mA; near rail at the microamp loads a servo signal input presents), through R1–R8 to the SIG pins.
5. The servo interprets a 50 Hz pulse train, nominally 1.0–2.0 ms pulse width, 1.5 ms = mid-range, and drives its horn accordingly.

Why logic must be up before VSERVO (and one caveat)#

If VSERVO rises while the A inputs are floating (PMOD unplugged, or host pins tri-stated), the buffer inputs are undefined. TI's own layout guideline for this device says unused inputs "must not ever be left floating" because the result is undefined operational states. Undefined states on Y1–Y8 mean arbitrary pulse-like edges on eight servo signal lines: servos can twitch, jump, or slew with no command ever having been issued. Therefore: host connected and driving all eight lines to a defined level (idle low) before VSERVO is applied, and VSERVO removed before the host is detached.

The caveat: with VSERVO absent and the host driving 3.3 V highs, the input voltage exceeds VCC (= 0 V), which is an input-clamp condition — the datasheet limits input clamp current to ±20 mA when VI > VCC and warns that absolute-maximum exposure "for extended periods may affect device reliability." Current through the clamp also back-feeds the unpowered VSERVO net. The clean resolution is a software one: hold all eight PWM outputs logic low (not high, not floating) until VSERVO is confirmed present, then start the pulse trains. Idle-low is also the correct servo-signal idle state, so this costs nothing. How much clamp current actually flows through R-less inputs from a 3.3 V FPGA pin must be checked on the bench; do not leave PWM lines held high into an unpowered board as a habit.

3.3 The 6 V question — resolved by the U2 LDO#

Original finding (now fixed): the design allowed VSERVO up to 6 V while wiring it straight to the '541's VCC. The SN74HCT541 recommended operating VCC maximum is 5.5 V (absolute maximum 7 V). At 6 V the buffer sat between recommended and absolute maximum: not damaged, but TI does not guarantee datasheet parametrics there — "functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied." A second, subtler consequence: R17 pulled the enable inputs up to the same 6 V rail, and the '541's input absolute maximum is VCC + 0.5 V, so the cut-JP1 state was itself marginal.

The fix: U2 (AP2204K-5.0) regulates VSERVO down to a dedicated 5 V logic rail, V5BUF, which powers U1's VCC, its decoupling C1, and the R17 enable pull-up. The servo headers keep the full 5–6 V VSERVO rail, so 6 V high-torque servos remain supported — only the logic is regulated. Because both the supply and the enable pull-up now reference V5BUF, the '541 is inside its recommended range and its input abs-max is respected at any legal VSERVO.

Why an LDO and not simply "restrict the module to 5 V": the servo bank is part of the robot line, where 6 V packs are a legitimate torque choice. The AP2204K accepts up to 24 V in, so it introduces no new marginal spec of its own (a 6.0 V-max regulator would merely have relocated the problem). It drops out gracefully too: at VSERVO = 5.0 V the buffer load is only a few mA, so V5BUF sits within tens of mV of the input — still far above the 4.5 V recommended minimum.

Bench consequence: V5BUF should read ≈5.0 V regardless of whether you feed 5 V or 6 V into J3. That is the one-line proof the fix works (Phase B).

4. External interfaces#

There are no test points defined in the schematic. Until layout adds them, probe at component pads: U1 pin 20 (VCC), pin 10 (GND), pins 2–9 (A1–A8), pins 11–18 (Y8–Y1), pins 1/19 (~OE1/~OE2 = OE_N), the J3 terminals, and each header SIG pin downstream of its series resistor. Adding proper test points for VSERVO, GND, OE_N, and at least one A/Y pair is a layout-review recommendation from this document.

5. Component-by-component review#

5.1 Buffer and connectors#

5.2 The output-enable network: the bring-up safety default#

JP1 bridged grounds both active-low enables; the datasheet function table is unambiguous: either enable high forces all eight outputs to Z. With outputs hi-Z, a connected servo sees a floating SIG line and (in typical hobby servos) stops driving — it "releases," holding no position and making no commanded movement. R17 (10 kΩ to V5BUF) exists so that a cut JP1 leaves OE_N defined-high rather than floating.

For first bring-up this document recommends starting with JP1 cut (or never bridged, if the fab default can be ordered open): power sequencing, rail measurements, and PWM verification at the A inputs can all be done with every output guaranteed hi-Z, then the jumper is bridged for the one-servo test. Two things must be explicitly verified on the first article, not assumed:

1. With JP1 cut and the board powered, OE_N reads ≈ V5BUF (5 V) and every Y pin is hi-Z (no PWM leaks through; a servo plugged in does not move).
2. The chosen servos actually release on a floating signal line. Most do; some digital servos hold last position. Check with the servos on hand before relying on hi-Z as a safety state.

Datasheet disable time (tdis, ~OE to Y) is ≤ 38–50 ns depending on VCC and load — electrically instant. But hi-Z stops the command, not the motion already in progress and not the servo's internal power: JP1/OE is a signal kill, not an e-stop for a stalled or runaway mechanism. The VSERVO supply switch is the actual power kill.

5.3 Series resistors and enable pull-up#

Note on numbering: the schematic uses R1–R8 and then R17; R9–R16 do not exist in this revision. This is an observed generator artifact, not eight missing parts — the assembly review must not go hunting for R9–R16.

5.4 Decoupling and bulk capacitance#

Honest sizing note: ~30 µF of ceramic is decoupling, not an energy reservoir for 8-servo stall events. It handles the microsecond-to-millisecond edge; the millisecond-to-hundreds-of-millisecond stall transient is carried by the bench supply and its leads. A bulk electrolytic (hundreds of µF) at J3 or on the supply end of the leads is a reasonable bench addition and a layout-review question for the next revision.

5.5 Schematic-only items#

That is the complete reference-designator set: U1, J1, J3, J4–J11, JP1, R1–R8, R17, C1–C6, U2, and the three power flags.

6. The 8-servo current budget — do this arithmetic before choosing a supply#

All per-servo numbers below are typical hobby estimates, not guaranteed datasheet values; measure the actual servos before trusting any margin.

Compare against the design's own current path:

• J3 screw terminal: Phoenix MKDS 1,5-class terminals are typically rated in the 13.5–17.5 A range per pole — the exact MPN is still TBD in the design, so this must be confirmed from the Phoenix datasheet. Eight SG90s at stall (≤ 8 A) fit; eight MG996R-class at stall (16–24 A) exceed the typical rating of this terminal class.
• Servo header V+ pins: generic 2.54 mm square-pin contacts are typically rated ~3 A each. Each header carries only its own servo, so an SG90 is comfortable and an MG996R-class stall (2–3 A) sits at the contact's rating with no margin.
• PCB traces: layout has not started; there are no trace ratings to compare. The layout must route VSERVO from J3 to the eight headers as a pour or very wide trace sized for the full bank current, and this guide's numbers should be an input to that layout review.
• The bench supply is the only current limiter on the rail in this revision (polyfuse/per-channel limiting is an open decision). Size and limit it deliberately.

Practical conclusion: the module as designed is an 8× micro-servo bank, or a partially-populated standard-servo bank. Running eight MG996R-class servos to stall simultaneously is outside the credible connector budget and must not be attempted; if the application needs it, that is a redesign (XT30-class input, per-channel or bank protection), not a bench configuration.

7. Datasheet summary and design interpretation#

Servo electrical behavior (pulse format, stall current, brown-out threshold) is not covered by any datasheet on this board — it depends entirely on the servos the user plugs in, and the bench record must identify them by exact model.

8. Expected values before bench testing#

9. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin 1 at ~OE1) and that the ordered part is SN74HCT541DW — an HC541 (non-T) substitute has CMOS thresholds (VIH ≈ 3.5 V at 5 V) and breaks the 3.3 V level shift entirely; this is the single most damaging plausible substitution.
• Verify J1 pin-1 orientation against the host PMOD socket before first mating; a flipped plug rearranges PWM/GND/3V3.
• Verify J3 polarity marking on silk (layout to-do) and on the harness. There is no reverse protection.
• Confirm each J4–J11 is SIG/VSERVO/GND in pin 1/2/3 order, and that silk marks SIG (layout to-do).
• Measure R1–R8 = 100 Ω and R17 = 10 kΩ before power; a reel swap between the two values disables outputs (100 Ω pull-up is irrelevant, but 10 kΩ series resistors still work into a servo's high-Z input — the truly silent failure is 100 Ω where 10 kΩ belongs at R17, which is harmless with JP1 bridged and only matters when cut, so check it now, not later).
• Confirm JP1 state matches the intended bring-up plan (this guide: start cut).
• Confirm C2–C4 are the 25 V parts, not a lower-voltage lookalike.
• Confirm R9–R16 absence is expected (numbering gap, section 5.3).
• At layout review: VSERVO pour sizing per section 6, test points per section 4, silkscreen polarity/SIG marks, and the polyfuse decision.

10. Ordered bench-test procedure#

Stop at the first abnormal result. Record every step with board serial, supply and servo identities, equipment IDs, ambient, and operator. Two bench contexts are covered; run A–C identically in both, then continue in whichever context the module will actually live.

Context (a) — PMOD host FPGA: host board (e.g. AruviX ECP5) generates the eight PWM channels. Grounds: host GND reaches the module through J1 pins 5/11; the servo supply return lands on J3 pin 2; they join on the module. Keep the servo supply leads short and do not let the servo return find a second path through the host's USB/programmer ground — if the servo supply and the host supply share a bench earth, verify with a clamp meter or shunt that servo return current flows in the J3 lead, not through the PMOD.

Context (b) — standalone: a bench 3.3 V-logic PWM source (function generator or logic board) drives J1's PWM pins, with its ground tied to a J1 GND pin; a separate current-limited 5–6 V supply feeds J3. Tie the two supplies' grounds together at the module (they meet there anyway through the board); never drive A inputs from a source whose ground is not connected. Any A input not driven in this context must be strapped to GND — TI forbids floating inputs, and a floating channel can twitch its servo.

A. Unpowered inspection and resistance tests#

1. No supplies, no host, no servos connected. Complete the section 9 checklist under magnification.
2. Measure VSERVO-to-GND resistance at J3, both meter polarities. Expect high/charging (capacitors); investigate any hard short before power.
3. Measure OE_N: JP1 bridged → ≈ 0 Ω to GND; JP1 cut → ≈ 10 kΩ to VSERVO and open to GND.
4. Buzz each SIG pin to its U1 Y pin: ≈ 100 Ω. Buzz adjacent SIG pins to each other: open (catches Y-pin solder bridges).
5. Buzz each header pin 2 to J3 VSERVO and pin 3 to GND.
6. Buzz each J1 PWM pin to its U1 A pin (direct connection, ≈ 0 Ω).

B. First power, no servos, outputs disabled#

1. JP1 cut (or confirmed open). No servos fitted. Bench supply set to 5.0 V, current limit 100 mA, connected to J3 with correct polarity.
2. Context (a): host attached first, all eight PWM outputs configured and idling low. Context (b): PWM source attached, outputs low, grounds tied.
3. Apply VSERVO. Supply current should be far below the limit (µA–low mA). A supply hitting 100 mA with no servos is abnormal — stop.
4. Verify U1 VCC = 5.0 V, OE_N ≈ 5.0 V, and every Y/SIG pin hi-Z/quiet.
5. Start the PWM trains (1.5 ms at 50 Hz on all channels). Verify clean 3.3 V waveforms at the A pins and no PWM at any SIG pin (outputs disabled). This proves the OE safety state.
6. Power down VSERVO (before touching anything else).

C. Outputs enabled, still no servos#

1. Bridge JP1. Repeat B.2–B.3.
2. With PWM running, verify each of the eight SIG pins shows the 50 Hz, 1.5 ms pulse swinging ≈ 0 V to ≈ 5 V. Check channel mapping: toggle one channel at a time from the host and confirm PWMn appears at J(3+n) and nowhere else.
3. Verify OE_N ≈ 0 V. Power down.

D. ONE SERVO FIRST#

1. VSERVO off. Fit one known servo (identify the exact model; prefer an SG90-class micro for first power) on J4, horn removed or mechanism clear. Hands clear from here on.
2. Supply still 5.0 V; raise the current limit to ~1.2 A (above one micro servo's stall, below anything destructive).
3. Host commands channel 1 to a constant 1.5 ms mid-range before power.
4. Apply VSERVO. Expect one settling movement to mid-range, then a holding current in the tens of mA. Sustained near-limit current means a stalled or faulty servo — power down and investigate.
5. Command slow sweeps (1.0 → 2.0 ms). Watch supply current and VSERVO on the scope; note the step-transient peaks.
6. Deliberately gently load the horn by hand-adjacent means only if the mechanism design makes that safe; otherwise measure stall current with a proper fixture. Record the measured stall — this number recalibrates the section 6 budget for the actual fleet.
7. Power down. Move the servo across J5…J11, repeating steps 3–5 briefly on each header, to prove all eight channels drive a real load.

E. Bank population and transient behavior#

1. VSERVO off between every connector change (never hot-plug). Populate two, then four, then eight servos, raising the current limit at each step to cover measured moving current with margin but staying below the J3 terminal's confirmed rating and below 8× measured stall.
2. At each population level: all channels to mid-range, then a simultaneous step command to all channels. Capture VSERVO at J3 and at the farthest header during the step; record the dip. A dip that resets servos or glitches U1 (SIG corruption) is the brown-out failure the bulk caps and supply leads must be fixed to prevent — stop and improve the supply path before proceeding.
3. Thermal: run a continuous motion pattern for 30–60 minutes at full population; check J3 screws, header pins, and the VSERVO copper (once a real layout exists) by touch-safe IR or thermocouple. Warm is expected; too-hot-to-touch contacts are a stop.
4. OE under load: JP1 is a solder jumper, not a switch — never rework it on a powered board. If a runtime-disable test is wanted, perform it by pulling OE_N high through a clip lead to VSERVO with hands clear, and verify all servos release. Note for the next revision: a proper OE header/MOSFET would make this test (and the safety state) switchable.

F. 6 V operation (now a supported mode — verify the LDO holds)#

Only after A–E pass at 5.0 V: raise VSERVO to 6.0 V with servos fitted.

1. Confirm V5BUF stays ≈5.0 V at U1 pin 20 / C6. This is the whole point of U2 — the buffer rail must not follow the servo rail. Log both numbers.
2. Re-run the channel checks (C) and a step test (D) at 6.0 V; servo torque and step current will be higher, V5BUF should be unchanged.
3. Watch U2's package temperature. It only carries the buffer's few mA, so it should stay near ambient; a warm SOT-23-5 means something is loading V5BUF.
4. Drop VSERVO to 4.8 V (a discharged 4-cell NiMH case) and confirm V5BUF is still ≥4.5 V — the '541's recommended minimum. This is the dropout edge.

11. Troubleshooting map#

12. Bench record template#

13. Review conclusion#

The architecture is sound and appropriately minimal for its teaching purpose: one HCT-threshold buffer performs the 3.3 V-to-5 V level shift, the servo rail is kept off the PMOD, the buffer has its own regulated rail so the servo pack voltage never reaches the logic, the enable network has a defined safe (hi-Z) state, and the bulk capacitors acknowledge servo transient behavior. The schematic is ERC-clean, the layout is DRC-clean, and every reference designator has a coherent role.

The principal open risks, in order: (1) nothing exists yet beyond a schematic — no layout, no board, no bench evidence, so every number here is a target; (2) the former 6 V-over-recommended-VCC finding is resolved: U2 gives the buffer its own regulated 5 V rail (V5BUF), so 5–6 V servo packs are all legal and the enable pull-up no longer sits above the '541's input abs-max — this now needs bench confirmation (Phase F) rather than a design decision; (3) the current path is unprotected — no fuse, no reverse protection, a deferred polyfuse decision — and the 8× stall budget shows standard-size servos can exceed the credible connector ratings, so the module's supported servo class must be stated in the release documentation; (4) the input-clamp/back-power path when logic drives an unpowered board makes the "PWM idle-low until VSERVO present" rule load-bearing and it should be promoted into the host HDL deliverable; (5) JP1 as a solder jumper makes the safe hi-Z state non-switchable at runtime — adequate for bring-up, worth revisiting for the classroom use case. None of these blocks fabrication; all of them must be closed or consciously accepted before the board is called released.