← AXA-003

Circuit review & bench-test guide

AXA-003 — Motor encoder interface PMOD module

Document purpose#

This document explains the axa-003-encoder PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py), the module README, and the actuator-line overview in ../README.md.

This is an unfabricated prototype design. Status on record: schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, no board built, no BOM purchased, and no bench evidence of any kind exists. Every voltage, frequency, and threshold below is a design target derived from the schematic and manufacturer datasheets — a plan for what to verify, not proof that an assembled board works or is safe. Where a number could not be confirmed from a fetched datasheet, that is stated explicitly.

1. What the board does#

The board is a six-channel digital input conditioner on the PMOD form factor (target outline 20 × 40 mm, 2-layer, 0603 passives). It accepts two quadrature encoder pairs (E1A/E1B and E2A/E2B) from N20/JGA25-class gearmotor encoders plus two spare hall/limit inputs (H1/H2). Each channel is pulled up 10 kΩ to 3V3 (encoder outputs are often open-collector), low-pass filtered by 1 kΩ + 10 nF (fc ≈ 16 kHz, to strip motor-wire noise), squared up by one gate of a Nexperia 74HC14 hex inverting Schmitt trigger, and driven to the PMOD through a 100 Ω series resistor. The FPGA host performs quadrature decode in fabric.

The board has no microcontroller, no motor driver, and no motor power path: per the actuator-line rule, motor power never flows through the PMOD — this module carries 3.3 V logic only. The motor that spins the encoder is driven by a separate board (e.g. AXA-001) or a separate bench supply.

Every channel is inverted by the Schmitt stage. Quadrature decoding is insensitive to A/B inversion, but level-sensitive uses of H1/H2 (hall, limit switch, index) must invert in fabric, and the inversion interacts with the perceived rotation direction (Section 10.E).

Functional block diagram#

Encoder 1 ──> J2 (3V3/GND/A/B) ──┐
Encoder 2 ──> J3 (3V3/GND/A/B) ──┤   per channel, x6:
Hall/limit ─> J4 (H1/H2/GND)  ───┤
                                 v
             3V3 ──10k (R1-R6)──> <CH>_RAW
                                 │
                          1k (R7-R12) series
                                 │
             <CH>_F ── 10nF (C1-C6) to GND      fc ~16 kHz
                                 │
                                 v
                     74HC14 U1 gate (INVERTS)
                                 │
                        100R (R13-R18) series
                                 │
                                 v
        PMOD J1: 1 E1A  2 E1B  3 E2A  4 E2B  7 H1  8 H2
                 (all module-driven, all = NOT(input))

        3V3/GND from PMOD J1 pins 5/6/11/12; C7 100nF decouples U1

2. Safety and scope boundaries — bench testing with a spinning motor#

This is an encoder interface board, but it cannot be meaningfully bench tested without a motor spinning the encoder shaft. Moving-machinery rules apply even though the board itself only carries logic signals.

• First power-up is always on a current-limited bench supply. Set the 3V3 logic supply limit to 50 mA or less for the first application of power; the expected quiescent draw of this board is microamps (Section 7).
• The motor has stall and shorted-rotor current far above its running current. Typical estimates (verify against your motor's datasheet, do not trust these numbers for a specific unit): N20-class gearmotors stall at roughly 0.36–1.6 A depending on winding and voltage; JGA25-class motors can stall at up to about 4 A. Set the motor supply current limit accordingly and never power the motor from an unlimited supply on the bench.
• Never hot-plug encoder or motor leads while powered. Plugging J2/J3 hot can momentarily short 3V3 to GND through misaligned pins, and hot motor leads arc and inject inductive kickback into the wiring bundle shared with the encoder signals.
• Rail sequencing: apply the 3.3 V logic rail (board + encoder supply) before the motor rail, and remove the motor rail first. The encoder hall sensors are powered from this board's 3V3; spinning them unpowered is harmless, but powering the motor first means the shaft is already moving when you start handling logic connections.
• "Hands clear" convention: before commanding the motor that drives the encoder shaft (from the FPGA, a driver board, or by connecting the motor supply), announce/confirm hands, probes, and loose wires are clear of the shaft, coupler, and gearbox. Gearmotor output shafts produce high torque; loose scope leads wrap around shafts. Secure the motor mechanically before any powered test — a motor spinning free on the bench walks and falls.
• Encoder socket miswiring kills hall sensors. J2/J3 pin order is 3V3 / GND / A / B. N20/JGA25 encoder breakout wire orders vary between vendors; swapping 3V3 and GND destroys the encoder's hall ICs. Buzz out the harness against the encoder breakout silkscreen before first connection.
• A clean quadrature waveform is not EMC, safety, or environmental qualification. Passing every test in this guide proves signal conditioning behavior on one bench, nothing more.

3. Signal path and conditioning behavior#

1. With nothing connected to J2/J3/J4, each 10 kΩ pull-up (R1–R6) holds its <CH>_RAW net at 3V3. The Schmitt inputs sit high, so all six PMOD lines idle low (inverted).
2. An open-collector encoder output pulls <CH>_RAW low; a push-pull encoder output drives it both ways. Either is compatible with the pull-up.
3. The 1 kΩ series resistor (R7–R12) and 10 nF capacitor (C1–C6) form the noise filter, fc = 1/(2π·1 kΩ·10 nF) ≈ 15.9 kHz.
4. The filter is asymmetric with open-collector encoders. Falling edge: the encoder discharges the capacitor through 1 kΩ only (τ ≈ 10 µs). Rising edge: the capacitor charges through the pull-up plus the series resistor, 10 kΩ + 1 kΩ = 11 kΩ (τ ≈ 110 µs). Reaching a typical 3.3 V VT+ (~55% of rail, Section 7) takes roughly 0.8·τ ≈ 90 µs, so the usable channel frequency with a true open-collector encoder is on the order of 5 kHz with significant duty-cycle distortion, not the filter's 16 kHz corner. With push-pull encoder outputs both edges see ~10 µs and the corner frequency governs. This must be measured (Section 10.D); the README's "MHz edge rates" refers to what the fabric decoder can accept, not what this analog front end passes.
5. The 74HC14 gate converts the slow RC edge into a clean, jitter-free, inverted logic edge (the whole reason a Schmitt part is used: its input tolerates unlimited rise/fall times, which an ordinary CMOS gate does not).
6. The 100 Ω series resistor (R13–R18) damps the trace/cable to the PMOD and limits fault current if a PMOD pin is misdriven from the host side.

4. Interfaces and pin maps#

PMOD J1 pin map (all lines inverted relative to the connector inputs):

Channel-to-gate assignment inside U1 (74HC14, SOIC-14):

U1 power: pin 14 = 3V3, pin 7 = GND (unit 7 in the schematic generator). There are no test points defined in the current schematic; adding TPs for 3V3, GND, one _RAW, one _F, and one PMOD-side net per encoder is a layout recommendation, because every measurement below otherwise requires probing component pads.

5. Component-by-component review#

5.1 Active conditioning#

74HC14 numbers used in this review (Nexperia datasheet Rev. 10, 2024-02-29): VCC operating 2.0–6.0 V; absolute maximum VCC 7 V, input clamp current ±20 mA, output clamp current ±20 mA, output current ±25 mA per pin, ICC/IGND 50 mA total, Ptot 500 mW. Thresholds are only specified at VCC = 2.0, 4.5, and 6.0 V — there is no 3.3 V column:

At 3.3 V, interpolation suggests VT+ ≈ 1.8 V typical and VT− ≈ 0.9–1.0 V typical, but these are estimates, not datasheet guarantees — measure them (Section 10.C) and treat only the 2.0/4.5 V rows as manufacturer-backed. Propagation delay at VCC = 4.5 V is 15 ns typical / 25 ns max (slower at lower VCC: 41 ns typical at 2.0 V); quiescent ICC is 2.0 µA max at 25 °C.

5.2 Per-channel passives (one set per channel; see table in Section 4 for assignment)#

5.3 Power, decoupling, and connectors#

Note: J2/J3/J4 MPNs are recorded as TBD in the schematic. They must be selected and the footprints verified before layout; this guide cannot review parts that have not been chosen.

6. Datasheet summary and design interpretation#

Encoder and motor figures used in this guide (N20/JGA25 stall currents, typical CPR values) are class-typical estimates, not datasheet values — the specific encoder/motor chosen for the bench must be looked up and its numbers substituted in Section 8 before testing.

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Confirm U1 is the HC part (74HC14D,653), not 74HCT14 — the HCT variant is out of spec below 4.5 V supply. Check pin-1 orientation against the SOIC-14 footprint.
• Verify the six-gate channel assignment against Section 4 (unit 4 uses input pin 9 / output pin 8 — the pin order reverses on that side of the package; a netlist error here swaps input and output on one channel).
• Confirm no value mixups between the three resistor values (10 k / 1 k / 100 Ω) and between C1–C6 (10 nF) and C7 (100 nF); all share the 0603 footprint and are trivially interchangeable by a placement error.
• Measure R1–R18 in circuit before first power where practical (10 k pull-ups read near 10 k against an unpowered CMOS input; 1 k and 100 Ω read true).
• Buzz J2 and J3 pin 1 to the 3V3 net and pin 2 to GND; then buzz the mating encoder harness against the encoder breakout's silkscreen. Do this for every new encoder/harness, not once.
• Confirm J1 orientation and that pins 9/10 are genuinely unconnected.
• Confirm C7 lands adjacent to U1 pin 14 in layout review (layout does not exist yet — carry this item forward).
• Confirm #FLG01/#FLG02 do not appear in BOM/placement outputs.

9. Bench contexts and grounding#

Two setups are covered; the procedure in Section 10 states which applies.

(a) PMOD host context. The module plugs into an FPGA host board (AruviX ECP5 or any PMOD host). 3V3 and GND come from the host; the host's supply current limit protects the module. The motor is driven from a separate current-limited motor supply (directly, or through a driver module). Ground is shared through the PMOD connector; the motor supply return must be joined to that same ground at one point (at the driver module or host ground post), or encoder signals will ride on whatever offset the motor return develops. Scope ground clips go to the host/module GND only.

(b) Standalone bench context. The module's 3V3 comes from a lab supply (set 3.3 V, current limit ≤ 50 mA) wired to the PMOD 3V3/GND pins via a breakout; a second, separate current-limited supply drives the test motor (limit per Section 2 stall estimates). The two supplies are floating relative to each other until you deliberately join their returns at the module GND — do so with one wire, at one point. An earth-referenced scope ground clip defines earth for the whole setup the moment it touches module GND; connect it only to GND and never to a motor lead.

In both contexts: logic rail on first, motor rail second; motor rail off first, logic rail off last.

10. Ordered bench-test procedure#

Stop at the first abnormal result. Record every measurement with board serial, encoder/motor identity (with their real datasheet numbers substituted into Section 8), equipment IDs, and operator.

A. Unpowered inspection and resistance tests#

1. Nothing connected: no host, no supplies, no encoders, no motor, no scope.
2. Complete the Section 8 checklist under magnification.
3. Measure 3V3-to-GND resistance at J1 in both meter polarities. A CMOS part plus pull-ups should read high (tens of kΩ or more, settling as meter capacitance charges); investigate anything under ~1 kΩ before power.
4. Measure each PMOD signal pin to GND and to 3V3: no hard shorts.
5. Buzz each J2/J3/J4 contact to its net (Section 4 tables). Verify J2/J3 pin 1 = 3V3, pin 2 = GND — this is the encoder-killing swap.
6. Buzz the encoder harness separately, then the harness plus encoder breakout documentation. Do not trust wire colors.

B. First power-up, no encoders, no motor#

1. Standalone context (9b): 3.3 V, current limit 50 mA, nothing in J2/J3/J4.
2. Apply power. Supply current must be well under 1 mA (target: µA-level). Higher current means a short, a reversed U1, or a wrong part — stop.
3. Verify 3.3 V at U1 pin 14 relative to pin 7.
4. Verify each <CH>_RAW node reads ~3.3 V and each PMOD signal pin reads logic low (inverted idle). Any channel idling high has an open pull-up, a solder problem at its gate, or a swapped gate pin assignment — stop.

C. Schmitt threshold and filter verification (one channel, then spot-check the rest)#

1. Still no motor. Drive one channel's connector input (e.g. J2 pin 3, E1A_RAW) from a function generator or a bench supply through a 1 kΩ protective resistor.
2. Slow-ramp threshold test: ramp the input slowly (≤ 1 V/s) from 0 V to 3.3 V and back while watching the corresponding PMOD output. Record the input voltage at which the output falls (that is VT+) and at which it rises again (VT−). Expect roughly 1.8 V and 1.0 V per the interpolated estimates, and require the measured window to sit between the datasheet's 2.0 V-column and 4.5 V-column limits (Section 5.1); anything outside that envelope means a wrong or damaged part. There must be exactly one clean output transition per threshold crossing — chatter here indicates a damaged gate or an open filter capacitor.
3. Filter test: apply a 3.3 Vpp square wave in push-pull mode; confirm the PMOD output follows (inverted) at 1 kHz, and observe attenuation and delay growing toward the ~16 kHz corner. Then, if the generator supports open-drain mode (or via a small-signal NPN/NMOS pulling the node low), repeat and record the duty-cycle distortion caused by the asymmetric 10 µs / 110 µs time constants. Record the maximum frequency at which the output still toggles rail-to-rail — this is the board's real channel bandwidth for open-collector encoders and must be compared against the Section 8 frequency-vs-RPM math for your motor before any speed test.
4. Spot-check at least one more channel per group (one of E2A/E2B, one of H1/H2) at a single frequency.

D. Quadrature capture with the encoder spun at speed#

1. Attach encoder(s) to J2/J3 (power off, Section 2). Power the logic rail; record the new supply current (encoder hall draw).
2. Mount the motor securely. Connect the motor to its current-limited supply (or driver module). Hands clear. Apply the motor rail at low voltage.
3. Phase relationship: two-channel scope capture of E1A and E1B at the PMOD at a steady low speed. Verify square waves at the same frequency with approximately 90° phase offset. Record the actual phase error — cheap magnetic encoders can deviate noticeably, and the fabric decoder's glitch filter budget depends on it.
4. Edge cleanliness, before vs after conditioning: capture the same edge simultaneously at <CH>_RAW (or <CH>_F) and at the PMOD pin. The raw node shows the RC-rounded, possibly noisy edge; the PMOD side must show a single monotonic fast edge (74HC14 transition time is nanoseconds) with no double-triggering. Any extra PMOD edges per raw edge means noise exceeding the hysteresis window — investigate wiring/grounding before blaming parts.
5. Frequency vs RPM math: at two or three known speeds (from a tachometer or the driver's commanded speed), measure the channel frequency and check f = (RPM/60) × PPR using your encoder's real pulses-per-revolution at the shaft the encoder observes (motor shaft, not gearbox output — a 7 PPR motor-shaft encoder behind a 100:1 gearbox gives 700 PPR at the output shaft). Then sweep to maximum motor speed and confirm the frequency stays below the bandwidth limit measured in step C.3; if it does not, counts will be silently lost and closed-loop control built on this board will be wrong at speed.
6. Repeat 3–5 for the second encoder channel pair on J3.

E. Direction convention and inversion check#

1. The Schmitt stage inverts both A and B, which preserves the quadrature sequence — but the apparent direction seen by the fabric decoder depends on the A/B lead-lag convention, the encoder vendor's phase assignment, the harness wiring, and this inversion. None of these can be assumed.
2. Rotate the shaft in a physically documented direction (e.g. clockwise viewed from the gearbox output face) by hand or at low motor voltage. Record which channel leads at the PMOD (E1A leading E1B, or the reverse).
3. Document this as the module's direction convention: "physical CW at the output shaft = <A leads B / B leads A> at the PMOD, for encoder model X wired per harness Y". Any change of encoder model or harness invalidates the record.
4. For H1/H2 only: verify polarity explicitly with a static test (hold the limit switch closed / magnet present, read the PMOD pin). These lines are level-sensitive and the inversion is not self-cancelling as it is for quadrature — fabric must invert them.

F. PMOD host integration#

1. Move to context 9a. With the host unpowered, plug the module; inspect alignment (offset-by-one insertion is the classic PMOD failure).
2. Power the host; confirm the host 3V3 rail is healthy and the module idles per step B.4.
3. Configure the six FPGA pins as inputs only. Confirm in constraints before loading a bitstream — a host pin misconfigured as an output fights U1 through 100 Ω at ~33 mA, beyond the gate's ±25 mA rating.
4. Run the quad_decoder fabric core (when it exists — the HDL deliverable is still open per the README) against a slow hand-rotation and verify the count direction matches the Section 10.E convention.
5. Repeat the D.5 speed sweep while comparing fabric counts against scope-measured edge counts over a fixed gate time.

11. Troubleshooting map#

12. Bench record template#

13. Review conclusion#

The architecture is simple and appropriate: passive pull-up and RC filtering per channel feeding a hex Schmitt inverter is the standard, robust front end for open-collector encoder outputs, and the 100 Ω series resistors give both protection and a useful diagnostic split point. The design's honesty about inversion (every channel is NOT(input)) is carried through the schematic comments and must be carried through fabric code and direction documentation.

The principal open risks, in order: (1) nothing has been built — there is no layout, no BOM buy, and no bench evidence, so everything in this guide is untested; (2) the asymmetric open-collector rise path (11 kΩ · 10 nF ≈ 110 µs) plausibly caps usable channel frequency near single-digit kHz, which may conflict with high-RPM motor-shaft encoders and must be measured against the chosen motor before the "MHz-rate decode" lesson is demonstrated at real speed; (3) the 74HC14's thresholds are not specified at 3.3 V and must be measured, not assumed; (4) J2/J3/J4 connector MPNs are TBD, and the 3V3/GND pin order at J2/J3 is an encoder-destroying miswire hazard that only harness discipline mitigates; (5) the fabric quad_decoder core, its glitch filter, and the direction convention record do not yet exist, and the board cannot be called verified until fabric counts have been cross-checked against scope edge counts with a real motor spinning the encoder.