← AXA-001

Circuit review & bench-test guide

AXA-001 — TB6612FNG dual DC motor driver PMOD module

Document purpose#

This document explains the axa-001-dc-motor PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the actuator-line rules in ../README.md.

This design is unfabricated. Status is "schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, not released." No board has been built, no first-article exists, and no bench evidence of any kind has been recorded. Every voltage, current, and timing value below is a design target or a datasheet number to verify against real hardware, not proof that an assembled module works or is safe. The procedures are written so they can be executed unchanged on the first article.

1. What the board does#

The module is a two-channel brushed-DC motor driver PMOD peripheral built around the Toshiba TB6612FNG dual H-bridge. A host FPGA (AruviX ECP5 board or any PMOD Type 1 GPIO host) drives each channel with a direction pair (xIN1/xIN2) and a PWM input at up to 100 kHz, plus a shared STBY gate. Motor power (VM, 2.5–13.5 V) enters on a screw terminal only and never flows through the PMOD connector; the PMOD carries 3.3 V logic exclusively, and the motor and logic grounds join on this module.

The TB6612FNG has no fault output and no current-sense output — a documented exception to the actuator-line feedback rule. Nothing on this module reports overcurrent, thermal shutdown, or UVLO back to the host. A spinning motor proves only that one commanded state works; it does not prove the truth table, the standby gate, current capability, or thermal margin.

Functional block diagram#

PMOD host (3.3 V logic only)          Motor supply (bench PSU / battery)
        │                                        │
        v                                        v
   J1 PMOD plug                          J3 screw terminal
   PWMA AIN1 AIN2                        VMOT (2.5–13.5 V), GND
   PWMB BIN1 BIN2                            │
   STBY  3V3  GND                            ├── C1, C2 10 µF bulk
        │      │                             └── C3 100 nF HF bypass
        │      └── C4 100 nF (VCC)               │
        v                                        v
   R1 10k STBY pull-down ──────> U1 TB6612FNG dual H-bridge
   (drivers default OFF)         VCC = 3V3, VM = VMOT
                                 UVLO + TSD internal, no fault pin
                                     │              │
                                     v              v
                              J4 MOTOR A      J5 MOTOR B
                              AO1 / AO2       BO1 / BO2

There is no J2 in this design; the reference-designator sequence J1, J3, J4, J5 is intentional in the generator and should not be "fixed" during layout without updating this document.

2. Actuator safety boundaries (mandatory reading)#

This board drives motors: moving, energy-storing, inductive loads. The rules below are not optional style; each one maps to a real failure mode.

• First power-up always on a current-limited bench supply. Set the motor supply current limit below the TB6612FNG's 1.2 A/channel absolute maximum before anything is connected. A miswired bridge, a solder short, or a wrong truth-table state then becomes a limited event instead of a burned SSOP-24.
• Know your motor's stall current before you connect it. A stalled or shorted-rotor motor draws its full locked-rotor current continuously. Typical figures (verify the exact motor you own — vendors vary):
• N20-class micro metal gearmotors: roughly 0.36 A (LP), 0.67 A (MP), to 1.5–1.6 A (HP/HPCB) stall at 6 V per Pololu's published specifications. Only LP/MP windings stall inside the TB6612FNG's 1.2 A/channel rating; an HP winding at stall exceeds it.
• JGA25-370-class 25 mm gearmotors: published stall figures are commonly in the 1.2–2.5 A range at 12 V, and the hottest windings are estimated up to roughly 4 A. Treat these as typical estimates, not data; check the specific motor's datasheet (for example the Seeed JGA25-370 datasheet). Most JGA25-class motors are not safe stall loads for this driver.
• Never hot-plug motor leads while the board is powered. Breaking an inductive circuit at a screw terminal draws an arc and produces a voltage spike; making one can chatter. Power down, wire, torque the terminal, then power up.
• Flyback path must be verified, not assumed. The recirculation path is the H-bridge body diodes inside U1 (VF 1.0 V typical at 1 A). There are no external flyback diodes. Scope the outputs during PWM and during commanded stop from full speed and confirm output excursions stay within one diode drop of VM and GND. Long motor leads add inductance; keep first-spin leads short.
• External rail sequencing: bring the 3.3 V logic rail up before the motor rail, and take it down after the motor rail. With VCC absent the control inputs' −0.2 to 6 V absolute maximum still applies and the internal 200 kΩ pull-downs hold the inputs low, but an unpowered controller with a live VM is an unverified state — do not rely on it. VM present with VCC absent must be treated as a forbidden operating condition until measured.
• "Hands clear" convention for the first commanded spin: before STBY is ever driven high with a motor attached, fingers, hair, sleeves, probe leads, and loose cables are away from shafts, couplings, and anything mounted on them; the motor body is clamped or held in a fixture, not hand-held; and the person at the enable control announces it. Geared micro motors have little torque but couplings, wheels, and test rigs can still snag and whip.
• The green-wire rule of this line applies: PMOD carries logic only. Never jumper VMOT to any PMOD pin "for convenience" — the PMOD host was never designed to carry motor current, and 13.5 V on a 3.3 V FPGA bank is fatal to the host.
• A working spin is not EMC, safety, or environmental qualification. This is a curriculum prototype.

3. Power and control sequence#

1. With logic power applied and no host activity, R1 (10 kΩ) plus U1's internal 200 kΩ pull-down hold STBY low. Both bridges are in standby: outputs high-impedance, standby supply current ≤1 µA per the datasheet.
2. All control inputs (PWMA/B, AIN1/2, BIN1/2) also have internal 200 kΩ pull-downs, so a floating or unconfigured host reads as all-low, which is the stop state even if STBY were high.
3. Motor power arrives on J3; C1/C2 (2× 10 µF) supply PWM switching current and C3 (100 nF) handles high frequency at the driver.
4. The host drives STBY high (VIH ≥ 0.7 × VCC = 2.31 V at 3.3 V) to enable both bridges, then commands each channel with xIN1/xIN2/PWMx per the truth table in section 6.
5. Internal UVLO (low-voltage detection, 1.9 V typical detect / 2.2 V typical recover, datasheet design-target values) and thermal shutdown (175 °C typical, 20 °C hysteresis, design target) protect the die silently — no pin reports either event.

Two bench contexts#

(a) Plugged into a PMOD host FPGA board. The host provides 3.3 V and the logic ground reference through J1; only the motor supply is external on J3. Grounds join on this module, so the motor supply's negative lead becomes common with the FPGA ground — the motor bench supply must therefore be floating (a normal isolated lab supply) or share the same earth reference deliberately. Sequencing: power the FPGA board first (logic up), then enable the motor supply; disable the motor supply before removing FPGA power. Keep the host's bitstream in a known state (all module pins low or high-Z) before the motor supply is enabled.

(b) Standalone bench, no FPGA. A lab supply provides 3.3 V into a PMOD pin 6/12 (3V3) and pin 5/11 (GND) breakout, and a separate current-limited supply provides VM on J3. The two supplies share ground only through this module's ground plane — do not add a second ground bond elsewhere that turns motor return current into a loop through logic wiring. Control inputs are driven from jumper wires to 3V3/GND or from a signal generator (0–3.3 V, never 5 V: VIN absolute maximum is 6 V but the logic rail context is 3.3 V and a 5 V generator into a shared setup invites mistakes). Same sequencing rule: 3.3 V up first, down last.

4. Interfaces#

There are no series resistors on the PMOD lines: the sensor-line 100 Ω rule applies to module-driven lines only, and every line here is host-driven. There are also no test points in the rev 0.1 schematic — probing is at component pads and connector screws. Adding test points on VMOT, 3V3, STBY, AO1/AO2, and BO1/BO2 is a recommended layout-stage improvement.

5. Component-by-component review#

5.1 Driver and connectors#

Reversing a motor's two leads at J4/J5 is not a fault — it swaps CW/CCW meaning. Document which lead went to which screw in the bench record.

5.2 Passives#

6. TB6612FNG datasheet summary and design interpretation#

Primary references: Toshiba TB6612FNG product page and the TB6612FNG datasheet, 2012-11-01 revision (the generator's toshiba.semicon-storage.com/info/...20141001.pdf link now returns 404; confirm the latest revision on the Toshiba page before release). All numbers below were read from the 2012-11-01 datasheet.

H-SW control truth table (datasheet, to be verified on hardware)#

Note the asymmetry that surprises firmware authors: PWM low does not mean coast — it means short brake (slow-decay). Coast (high-Z) requires IN1 = IN2 = L or STBY low.

7. Expected values before bench testing#

All values are datasheet-derived targets for an unbuilt board.

8. Manual schematic and assembly review checklist#

• Verify U1 orientation (pin 1 index toward AO1 side) and that all 24 SSOP pins are wetted; inspect for 0.65 mm-pitch bridges under magnification.
• Confirm PGND1 (pins 3/4), PGND2 (pins 9/10), and GND (pin 18) are all soldered and all reach the common ground pour — the schematic joins them with one label each; layout must give motor return current a path that does not pass through pin 18.
• Confirm VM1/VM2/VM3 (pins 24/13/14) are all connected; the generator labels each separately.
• Measure R1 = 10 kΩ from STBY to GND before connecting a host.
• Verify C1/C2 (0805) and C3/C4 (0603) locations: C1–C3 on VMOT, C4 on 3V3. Flag C3's 16 V rating if VM above ~11 V will be used.
• Buzz the PMOD pinout against the table in section 4, especially that pins 6/12 are 3V3 and 5/11 are GND, and that pin 10 is truly unconnected.
• Confirm no continuity between VMOT and 3V3, VMOT and any PMOD signal, and 3V3 and GND.
• Check screw-terminal torque on J3/J4/J5 and that stranded motor leads are ferruled or tinned per your bench convention.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, motor identity (vendor, winding, measured terminal resistance), supplies, equipment IDs, ambient, and operator. Observe the hands-clear convention (section 2) before every first enable with a motor attached.

A. Unpowered inspection and resistance tests#

1. Nothing connected. Complete the section 8 checklist under magnification.
2. Measure resistance VMOT-to-GND and 3V3-to-GND in both meter polarities. Expect no hard short (MLCC charging kick then high resistance).
3. Measure AO1/AO2/BO1/BO2 to VMOT and to GND. Expect diode signatures from the body diodes in diode-test mode (~0.5–0.7 V meter reading), never 0 Ω.
4. Measure STBY to GND: 10 kΩ (R1, in parallel with U1's internal 200 kΩ — expect ≈ 9.5 kΩ).
5. Verify VMOT-to-3V3 is open.

B. Logic-only power-up (no motor supply, no motors)#

Standalone context: bench 3.3 V, current limit 50 mA, onto PMOD 3V3/GND. Host context: plug into the FPGA board with a bitstream that drives all module pins low.

1. Apply 3.3 V. Expect supply current ≤ ~1 µA-class (meter floor) with STBY low; investigate anything above a few mA immediately.
2. Confirm STBY reads ≈ 0 V, all outputs high-Z (a 10 kΩ pull to a test voltage on AO1 moves the node freely).
3. Drive STBY high (3.3 V). Supply current should rise to ~1.1 mA typ (≤ 2.2 mA). Outputs remain high-Z with IN pins low (stop state).
4. Return STBY low before proceeding.

C. Motor supply, no motors: truth table and STBY verification#

Connect the second, current-limited supply to J3 (suggest 6 V, limit 200 mA for this section — no load current should flow). Attach 10 kΩ test pull resistors from each output to a midpoint (or alternately to VM and GND) to make high-Z detectable. This section is mandatory for both channels.

1. STBY low: step IN1/IN2/PWM through all combinations. All four outputs must remain high-Z throughout (outputs follow the test pulls). This is the STBY high-Z verification.
2. STBY high, channel A: verify every row of the section 6 truth table at AO1/AO2 with a DMM/scope: IN1=H IN2=L PWM=H → AO1=VM−Vsat, AO2≈0 (CW); IN1=L IN2=H PWM=H → AO1≈0, AO2=VM−Vsat (CCW); PWM=L in either direction → both outputs low (short brake); IN1=IN2=H → both low (short brake); IN1=IN2=L → high-Z (stop).
3. Repeat step 2 completely for channel B at BO1/BO2.
4. Apply 20 kHz PWM to PWMA with IN1=H IN2=L and scope AO1: clean VM/GND square wave, edges monotonic. Watch VM supply current for shoot-through spikes at edges. Repeat for channel B.
5. Drop STBY low mid-PWM: outputs must go high-Z immediately.

D. First motor spin (one channel, one motor)#

Use an N20-class LP or MP motor first (stall 0.36–0.67 A at 6 V — inside the driver's continuous rating). Motor supply 6 V, current limit set to 0.8 A.

1. Power everything down. Wire the motor to J4. Torque the screws. Never change motor wiring with power applied.
2. Hands clear. Logic up, motor supply up, STBY high, then command CW at 50 % PWM. The motor should spin; note direction against lead colors.
3. Command CCW: direction reverses. Command PWM low: short brake (shaft resists by hand noticeably more than in stop). Command stop (L/L): shaft spins freely.
4. Sweep PWM duty 10–100 % at 20 kHz; speed should track monotonically.
5. Repeat on J5/channel B with the same motor.

E. Flyback and dynamic checks#

1. Scope AO1 and AO2 (and VM) during PWM at 50 % duty with the motor loaded by finger-braking the gearbox output (not the bare shaft). Output excursions must stay within roughly VM + 1.1 V and GND − 1.1 V (body-diode VF at 1 A is 1.0 V typ / 1.1 V max). Anything beyond that indicates lead inductance or a decoupling problem.
2. From full speed, command short brake and capture the VM bus: C1/C2 must absorb the regenerative pump-up without VM rising near 15 V abs max. With a bench supply that cannot sink current, expect some pump-up — quantify it; large motors or long decelerations may need bulk electrolytic or a different brake strategy.
3. Repeat with the longest motor leads the application will use.

F. Stalled-motor per-channel current test#

This test deliberately stalls a motor. Stay under the TB6612FNG's ~1 A continuous per-channel operating rating; use the supply current limit to enforce this, not good intentions.

1. Use an N20 LP or MP winding (expected stall 0.36–0.67 A at 6 V). Do not run this test with an HP N20 (~1.6 A) or JGA25-class motor at rated voltage — their stall currents exceed the driver's continuous rating. Datasheet reality check: the 1.2 A "average" and 3.2 A "peak" absolute maximums are a 100 % figure and a 10 ms single-pulse figure respectively; neither permits sustained stall above ~1.0 A operating.
2. Set the motor supply current limit to 1.0 A. Command CW at 100 % duty and mechanically lock the gearbox output with a clamp fixture (never fingers).
3. Record steady-state channel current, VM droop, and U1 package temperature every 30 s for 5 minutes or until temperature plateaus. Terminate at once if U1 exceeds ~100 °C surface, if current misbehaves, or if the motor smells hot — small motors cook at stall long before the driver does.
4. Repeat for channel B, then both channels stalled together at reduced VM if dual-stall behavior matters to the application: the datasheet dual-channel derating curve shows roughly 0.9–1.0 A per channel at 100 % duty, IC only, 25 °C — the small board makes this worse. Watch for silent TSD cycling (motors pulsing without command changes).

G. Host-context integration#

1. Repeat sections C and D with the FPGA host generating the signals from the pwm_gen HDL core (once written — it is still a release to-do).
2. Verify host reset/reconfiguration mid-spin: STBY must fall (R1's job) and motors must coast during FPGA reconfiguration. This is the single most safety-relevant integration behavior; record it explicitly.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is deliberately minimal and pedagogically coherent: one integrated dual H-bridge with internal dead time, flyback diodes, UVLO, and TSD; strict motor/logic power separation with grounds joined on the module; and a fail-safe standby default via R1. The datasheet supports 3.3 V logic directly and the PMOD carries no motor current, which protects the host by construction.

The honest weaknesses are equally clear. First, the design is unfabricated — nothing here has ever been measured. Second, the TB6612FNG reports no faults: TSD and UVLO are silent, so the bench supply's current limit is the only external protection and the host cannot know a channel has shut down; this is a documented line-rule exception, and the curriculum should say so out loud. Third, thermals are the main physical risk: the 20 × 40 mm outline is smaller than the smallest datasheet reference board, and dual-channel operation near 1 A per channel is at the edge of the derating curve — layout copper and a measured stall soak (section 9.F) must close this before release. Fourth, small BOM items remain open: C3's 16 V rating is marginal against a 13.5 V rail, the J3/J4/J5 screw-terminal MPN is still TBD, the generator's datasheet URL is dead, and the VCC decoupling is lighter than Toshiba's application diagram. Finally, motor selection is a safety parameter, not a preference: only LP/MP N20-class windings stall safely inside this driver's rating, and that constraint belongs on the silkscreen or at least in the README.